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https://github.com/brain-hackers/u-boot-brain
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2f78eae506
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
24 lines
387 B
C
24 lines
387 B
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_
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#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_
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#include <common.h>
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enum mxc_clock {
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MXC_ARM_CLK = 0,
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MXC_BUS_CLK,
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MXC_UART_CLK,
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MXC_ESDHC_CLK,
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MXC_I2C_CLK,
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};
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unsigned int mxc_get_clock(enum mxc_clock clk);
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#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */
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