mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
89c00f009c
Backport and squash below Linux 5.2 commits for R-Car Gen3:
Commit id * Summary line
6fffb98645e67b5 arm64: dts: renesas: r8a77990: ebisu: Add GPIO expander
b068ed6efe6244d arm64: dts: renesas: r8a77990: Fix SPDX license identifier style
96c25882252704d ! arm64: dts: renesas: r8a7796: remove unneeded sound #address/size-cells
71ac75dffdae2f8 arm64: dts: renesas: r8a77990: ebisu: Enable LVDS1 encoder
9a0ff5c727b60a3 arm64: dts: renesas: r8a77995: draak: Enable LVDS1 encoder
9130c15829846fa arm64: dts: renesas: ebisu: Fix adv7482 hexadecimal register address
191f7dcd1f5ea1f arm64: dts: renesas: r8a77965: add SSIU support for sound
a8f6110e64422d5 arm64: dts: renesas: ebisu: Enable VIN5
4162aa9db3d4469 arm64: dts: renesas: r8a77995: draak: Enable CAN0, CAN1
af965ba3248edde arm64: dts: renesas: r8a77990: Remove invalid compatible value for CSI40
1f4c123a98098cc arm64: dts: renesas: r8a77990-ebisu: Add BD9571 PMIC
474706117c2baa6 arm64: dts: renesas: ebisu: Add PMIC DDR0 Backup Power config
e2fa79de7ecbef4 arm64: dts: renesas: Update Ebisu and Draak bootargs
de8e8daaf7190ef arm64: dts: renesas: salvator-common: Sort node label
05f1d882d28b871 arm64: dts: renesas: r8a77995: draak: Fix EthernetAVB phy mode to rgmii
7a516e49d975311 arm64: dts: renesas: use extended audio dmac register
e3414b8c45afa5c arm64: dts: renesas: salvator-common: Add GPIO keys support
720066d17c973fd arm64: dts: renesas: r8a7795: Add CMT device nodes
99cb95103e2d058 arm64: dts: renesas: r8a77965: Add CMT device nodes
28a5c61b5136d58 arm64: dts: renesas: r8a77990: Add CMT device nodes
32d622f3290b2a1 arm64: dts: renesas: r8a77965: Remove reg-names of display node
(*) Patch id mismatch between Linux and U-Boot commit.
[!] Dropped changes in arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts,
since the file doesn't exist in the U-Boot tree.
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
526 lines
8.4 KiB
Plaintext
526 lines
8.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Draak board
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*
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* Copyright (C) 2016-2018 Renesas Electronics Corp.
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* Copyright (C) 2017 Glider bvba
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*/
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/dts-v1/;
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#include "r8a77995.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Renesas Draak board based on r8a77995";
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compatible = "renesas,draak", "renesas,r8a77995";
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aliases {
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serial0 = &scif2;
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ethernet0 = &avb;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = "serial0:115200n8";
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 50000>;
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brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
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default-brightness-level = <10>;
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power-supply = <®_12p0v>;
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enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
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};
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composite-in {
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compatible = "composite-video-connector";
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port {
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composite_con_in: endpoint {
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remote-endpoint = <&adv7180_in>;
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};
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};
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};
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hdmi-in {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&adv7612_in>;
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};
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};
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};
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hdmi-out {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_out: endpoint {
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remote-endpoint = <&adv7511_out>;
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};
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};
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};
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lvds-decoder {
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compatible = "thine,thc63lvd1024";
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vcc-supply = <®_3p3v>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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thc63lvd1024_in: endpoint {
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remote-endpoint = <&lvds0_out>;
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};
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};
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port@2 {
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reg = <2>;
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thc63lvd1024_out: endpoint {
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remote-endpoint = <&adv7511_in>;
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};
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};
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};
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x18000000>;
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};
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reg_1p8v: regulator0 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator1 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_12p0v: regulator1 {
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compatible = "regulator-fixed";
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regulator-name = "D12.0V";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_in: endpoint {
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remote-endpoint = <&adv7123_out>;
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};
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};
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};
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vga-encoder {
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compatible = "adi,adv7123";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7123_in: endpoint {
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remote-endpoint = <&du_out_rgb>;
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};
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};
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port@1 {
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reg = <1>;
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adv7123_out: endpoint {
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remote-endpoint = <&vga_in>;
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};
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};
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};
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};
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x12_clk: x12 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <74250000>;
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};
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};
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&avb {
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pinctrl-0 = <&avb0_pins>;
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pinctrl-names = "default";
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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status = "okay";
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio5>;
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interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&can0 {
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pinctrl-0 = <&can0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&can1 {
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pinctrl-0 = <&can1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&du {
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pinctrl-0 = <&du_pins>;
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pinctrl-names = "default";
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status = "okay";
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>,
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<&x12_clk>;
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clock-names = "du.0", "du.1", "dclkin.0";
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ports {
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port@0 {
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endpoint {
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remote-endpoint = <&adv7123_in>;
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};
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};
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};
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};
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&ehci0 {
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dr_mode = "host";
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status = "okay";
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};
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&extal_clk {
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clock-frequency = <48000000>;
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};
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&hsusb {
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dr_mode = "host";
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status = "okay";
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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composite-in@20 {
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compatible = "adi,adv7180cp";
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reg = <0x20>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7180_in: endpoint {
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remote-endpoint = <&composite_con_in>;
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};
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};
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port@3 {
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reg = <3>;
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/*
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* The VIN4 video input path is shared between
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* CVBS and HDMI inputs through SW[49-53]
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* switches.
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*
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* CVBS is the default selection, link it to
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* VIN4 here.
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*/
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adv7180_out: endpoint {
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remote-endpoint = <&vin4_in>;
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};
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};
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};
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};
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hdmi-encoder@39 {
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compatible = "adi,adv7511w";
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reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
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reg-names = "main", "edid", "packet", "cec";
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interrupt-parent = <&gpio1>;
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interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
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/* Depends on LVDS */
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max-clock = <135000000>;
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min-vrefresh = <50>;
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adi,input-depth = <8>;
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adi,input-colorspace = "rgb";
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adi,input-clock = "1x";
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adi,input-style = <1>;
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adi,input-justification = "evenly";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7511_in: endpoint {
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remote-endpoint = <&thc63lvd1024_out>;
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};
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};
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port@1 {
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reg = <1>;
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adv7511_out: endpoint {
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remote-endpoint = <&hdmi_con_out>;
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};
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};
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};
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};
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hdmi-decoder@4c {
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compatible = "adi,adv7612";
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reg = <0x4c>;
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default-input = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7612_in: endpoint {
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remote-endpoint = <&hdmi_con_in>;
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};
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};
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port@2 {
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reg = <2>;
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/*
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* The VIN4 video input path is shared between
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* CVBS and HDMI inputs through SW[49-53]
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* switches.
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*
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* CVBS is the default selection, leave HDMI
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* not connected here.
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*/
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adv7612_out: endpoint {
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pclk-sample = <0>;
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hsync-active = <0>;
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vsync-active = <0>;
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};
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};
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};
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};
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eeprom@50 {
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compatible = "rohm,br24t01", "atmel,24c01";
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reg = <0x50>;
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pagesize = <8>;
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};
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&lvds0 {
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status = "okay";
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clocks = <&cpg CPG_MOD 727>,
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<&x12_clk>,
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<&extal_clk>;
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clock-names = "fck", "dclkin.0", "extal";
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ports {
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port@1 {
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lvds0_out: endpoint {
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remote-endpoint = <&thc63lvd1024_in>;
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};
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};
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};
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};
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&lvds1 {
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/*
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* Even though the LVDS1 output is not connected, the encoder must be
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* enabled to supply a pixel clock to the DU for the DPAD output when
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* LVDS0 is in use.
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*/
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status = "okay";
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clocks = <&cpg CPG_MOD 727>,
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<&x12_clk>,
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<&extal_clk>;
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clock-names = "fck", "dclkin.0", "extal";
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};
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&ohci0 {
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dr_mode = "host";
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status = "okay";
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};
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&pfc {
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avb0_pins: avb {
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mux {
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groups = "avb0_link", "avb0_mdio", "avb0_mii";
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function = "avb0";
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};
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};
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can0_pins: can0 {
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groups = "can0_data_a";
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function = "can0";
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};
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can1_pins: can1 {
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groups = "can1_data_a";
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function = "can1";
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};
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du_pins: du {
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groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
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function = "du";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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i2c1_pins: i2c1 {
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groups = "i2c1";
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function = "i2c1";
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};
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pwm0_pins: pwm0 {
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groups = "pwm0_c";
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function = "pwm0";
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};
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pwm1_pins: pwm1 {
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groups = "pwm1_c";
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function = "pwm1";
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};
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scif2_pins: scif2 {
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groups = "scif2_data";
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function = "scif2";
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};
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sdhi2_pins: sd2 {
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groups = "mmc_data8", "mmc_ctrl";
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function = "mmc";
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power-source = <1800>;
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};
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sdhi2_pins_uhs: sd2_uhs {
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groups = "mmc_data8", "mmc_ctrl";
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function = "mmc";
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power-source = <1800>;
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};
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usb0_pins: usb0 {
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groups = "usb0";
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function = "usb0";
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};
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vin4_pins_cvbs: vin4 {
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groups = "vin4_data8", "vin4_sync", "vin4_clk";
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function = "vin4";
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};
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};
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&pwm0 {
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pinctrl-0 = <&pwm0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pwm1 {
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pinctrl-0 = <&pwm1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&rwdt {
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timeout-sec = <60>;
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status = "okay";
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};
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&scif2 {
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdhi2 {
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/* used for on-board eMMC */
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pinctrl-0 = <&sdhi2_pins>;
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pinctrl-1 = <&sdhi2_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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bus-width = <8>;
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mmc-hs200-1_8v;
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non-removable;
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status = "okay";
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};
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&usb2_phy0 {
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pinctrl-0 = <&usb0_pins>;
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pinctrl-names = "default";
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renesas,no-otg-pins;
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status = "okay";
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};
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&vin4 {
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pinctrl-0 = <&vin4_pins_cvbs>;
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pinctrl-names = "default";
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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vin4_in: endpoint {
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remote-endpoint = <&adv7180_out>;
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};
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};
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};
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};
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