mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
5aeab3bf5e
J721e has two instances of Cadence USB3 controller. Add DT nodes for the same. USB0 is configured to device mode and USB1 is configured to host mode. For now only high speed mode is supported. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
437 lines
12 KiB
Plaintext
437 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J721E SoC Family Main Domain peripherals
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*
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* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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&cbass_main {
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msmc_ram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x70000000 0x0 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x70000000 0x800000>;
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atf-sram@0 {
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reg = <0x0 0x20000>;
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};
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01900000 0x00 0x100000>; /* GICR */
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/* vcpumntirq: virtual CPU interface maintenance interrupt */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: gic-its@18200000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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smmu0: smmu@36600000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0x36600000 0x0 0x100000>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror";
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#iommu-cells = <1>;
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};
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secure_proxy_main: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x32c00000 0x00 0x100000>,
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<0x00 0x32400000 0x00 0x100000>,
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<0x00 0x32800000 0x00 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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main_pmx0: pinmux@11c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x0 0x11c000 0x0 0x2b4>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 0>;
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clock-names = "fclk";
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};
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main_uart1: serial@2810000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 278 0>;
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clock-names = "fclk";
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};
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main_uart2: serial@2820000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 279 0>;
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clock-names = "fclk";
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};
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main_uart3: serial@2830000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02830000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 280 0>;
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clock-names = "fclk";
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};
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main_uart4: serial@2840000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02840000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 281 0>;
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clock-names = "fclk";
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};
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main_uart5: serial@2850000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02850000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 282 0>;
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clock-names = "fclk";
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};
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main_uart6: serial@2860000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02860000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 283 0>;
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clock-names = "fclk";
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};
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main_uart7: serial@2870000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02870000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 284 0>;
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clock-names = "fclk";
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};
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main_uart8: serial@2880000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02880000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 285 0>;
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clock-names = "fclk";
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};
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main_uart9: serial@2890000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02890000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 286 0>;
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clock-names = "fclk";
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};
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main_sdhci0: sdhci@4f80000 {
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compatible = "ti,j721e-sdhci-8bit";
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reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
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assigned-clocks = <&k3_clks 91 1>;
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assigned-clock-parents = <&k3_clks 91 2>;
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bus-width = <8>;
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ti,otap-del-sel = <0x2>;
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ti,trm-icp = <0x8>;
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dma-coherent;
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};
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main_sdhci1: sdhci@4fb0000 {
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compatible = "ti,j721e-sdhci-4bit";
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reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
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assigned-clocks = <&k3_clks 92 0>;
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assigned-clock-parents = <&k3_clks 92 1>;
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ti,otap-del-sel = <0x2>;
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ti,trm-icp = <0x8>;
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dma-coherent;
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};
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main_r5fss0: r5fss@5c00000 {
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compatible = "ti,j721e-r5fss";
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lockstep-mode = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
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<0x5d00000 0x00 0x5d00000 0x20000>;
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power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
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main_r5fss0_core0: r5f@5c00000 {
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compatible = "ti,j721e-r5f";
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reg = <0x5c00000 0x00008000>,
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<0x5c10000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <245>;
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ti,sci-proc-ids = <0x06 0xFF>;
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resets = <&k3_reset 245 1>;
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atcm-enable = <1>;
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btcm-enable = <1>;
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loczrama = <1>;
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};
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main_r5fss0_core1: r5f@5d00000 {
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compatible = "ti,j721e-r5f";
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reg = <0x5d00000 0x00008000>,
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<0x5d10000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <246>;
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ti,sci-proc-ids = <0x07 0xFF>;
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resets = <&k3_reset 246 1>;
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atcm-enable = <1>;
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btcm-enable = <1>;
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loczrama = <1>;
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};
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};
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main_r5fss1: r5fss@5e00000 {
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compatible = "ti,j721e-r5fss";
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lockstep-mode = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
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<0x5f00000 0x00 0x5f00000 0x20000>;
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power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
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main_r5fss1_core0: r5f@5e00000 {
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compatible = "ti,j721e-r5f";
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reg = <0x5e00000 0x00008000>,
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<0x5e10000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <247>;
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ti,sci-proc-ids = <0x08 0xFF>;
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resets = <&k3_reset 247 1>;
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atcm-enable = <1>;
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btcm-enable = <1>;
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loczrama = <1>;
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};
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main_r5fss1_core1: r5f@5f00000 {
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compatible = "ti,j721e-r5f";
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reg = <0x5f00000 0x00008000>,
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<0x5f10000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <248>;
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ti,sci-proc-ids = <0x09 0xFF>;
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resets = <&k3_reset 248 1>;
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atcm-enable = <1>;
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btcm-enable = <1>;
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loczrama = <1>;
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};
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};
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c66_0: dsp@4d80800000 {
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compatible = "ti,j721e-c66-dsp";
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reg = <0x4d 0x80800000 0x00 0x00048000>,
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<0x4d 0x80e00000 0x00 0x00008000>,
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<0x4d 0x80f00000 0x00 0x00008000>;
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reg-names = "l2sram", "l1pram", "l1dram";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <142>;
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ti,sci-proc-ids = <0x03 0xFF>;
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resets = <&k3_reset 142 1>;
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};
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c66_1: dsp@4d81800000 {
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compatible = "ti,j721e-c66-dsp";
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reg = <0x4d 0x81800000 0x00 0x00048000>,
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<0x4d 0x81e00000 0x00 0x00008000>,
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<0x4d 0x81f00000 0x00 0x00008000>;
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reg-names = "l2sram", "l1pram", "l1dram";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <143>;
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ti,sci-proc-ids = <0x04 0xFF>;
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resets = <&k3_reset 143 1>;
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};
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c71_0: dsp@64800000 {
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compatible = "ti,j721e-c71-dsp";
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reg = <0x00 0x64800000 0x00 0x00080000>,
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<0x00 0x64e00000 0x00 0x0000c000>;
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reg-names = "l2sram", "l1dram";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <15>;
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ti,sci-proc-ids = <0x30 0xFF>;
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resets = <&k3_reset 15 1>;
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};
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usbss0: cdns_usb@4104000 {
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compatible = "ti,j721e-usb";
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reg = <0x00 0x4104000 0x00 0x100>;
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dma-coherent;
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power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
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clock-names = "usb2_refclk", "lpm_clk";
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assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
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assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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phy@4108000 {
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compatible = "ti,j721e-usb2-phy";
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reg = <0x00 0x4108000 0x00 0x400>;
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};
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usb0: usb@6000000 {
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compatible = "cdns,usb3";
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reg = <0x00 0x6000000 0x00 0x10000>,
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<0x00 0x6010000 0x00 0x10000>,
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<0x00 0x6020000 0x00 0x10000>;
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reg-names = "otg", "xhci", "dev";
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
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interrupt-names = "host",
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"peripheral",
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"otg";
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maximum-speed = "super-speed";
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dr_mode = "otg";
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};
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};
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usbss1: cdns_usb@4114000 {
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compatible = "ti,j721e-usb";
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reg = <0x00 0x4114000 0x00 0x100>;
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dma-coherent;
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power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
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clock-names = "usb2_refclk", "lpm_clk";
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assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
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assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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phy@4118000 {
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compatible = "ti,j721e-usb2-phy";
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reg = <0x00 0x4118000 0x00 0x400>;
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};
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usb1: usb@6400000 {
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compatible = "cdns,usb3";
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reg = <0x00 0x6400000 0x00 0x10000>,
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<0x00 0x6410000 0x00 0x10000>,
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<0x00 0x6420000 0x00 0x10000>;
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reg-names = "otg", "xhci", "dev";
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
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interrupt-names = "host",
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"peripheral",
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"otg";
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maximum-speed = "super-speed";
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dr_mode = "otg";
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};
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};
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ufs_wrapper: ufs-wrapper@4e80000 {
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compatible = "ti,j721e-ufs";
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reg = <0x0 0x4e80000 0x0 0x100>;
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power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 277 1>;
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assigned-clocks = <&k3_clks 277 1>;
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assigned-clock-parents = <&k3_clks 277 4>;
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ranges;
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#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
ufs@4e84000 {
|
|
compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
|
|
reg = <0x0 0x4e84000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
freq-table-hz = <0 0>, <0 0>;
|
|
clocks = <&k3_clks 277 0>, <&k3_clks 277 1>;
|
|
clock-names = "core_clk", "phy_clk";
|
|
assigned-clocks = <&k3_clks 277 1>;
|
|
assigned-clock-parents = <&k3_clks 277 4>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
};
|