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2f27c9219e
Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
46 lines
967 B
C
46 lines
967 B
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (C) 2020 Microchip Technology Inc.
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* Padmarao Begari <padmarao.begari@microchip.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
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#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
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#define CLK_CPU 0
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#define CLK_AXI 1
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#define CLK_AHB 2
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#define CLK_ENVM 3
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#define CLK_MAC0 4
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#define CLK_MAC1 5
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#define CLK_MMC 6
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#define CLK_TIMER 7
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#define CLK_MMUART0 8
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#define CLK_MMUART1 9
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#define CLK_MMUART2 10
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#define CLK_MMUART3 11
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#define CLK_MMUART4 12
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#define CLK_SPI0 13
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#define CLK_SPI1 14
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#define CLK_I2C0 15
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#define CLK_I2C1 16
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#define CLK_CAN0 17
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#define CLK_CAN1 18
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#define CLK_USB 19
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#define CLK_RESERVED 20
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#define CLK_RTC 21
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#define CLK_QSPI 22
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#define CLK_GPIO0 23
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#define CLK_GPIO1 24
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#define CLK_GPIO2 25
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#define CLK_DDRC 26
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#define CLK_FIC0 27
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#define CLK_FIC1 28
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#define CLK_FIC2 29
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#define CLK_FIC3 30
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#define CLK_ATHENA 31
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#define CLK_CFM 32
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#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
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