mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 12:46:17 +09:00
e7563aff17
The ddr code computes most things as 64-bit quantities and had some places in the middle that it was using phy_addr_t and phys_size_t. Instead we use unsigned long long through out and only at the last stage of setting the LAWs and reporting the amount of memory to the board code do we truncate down to what we can cover via phys_size_t. This has the added benefit that the DDR controller itself is always setup the same way regardless of how much memory we have. Its only the LAW setup that limits what is visible to the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
110 lines
2.6 KiB
C
110 lines
2.6 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include "ddr.h"
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unsigned int fsl_ddr_get_mem_data_rate(void);
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/*
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* Round mclk_ps to nearest 10 ps in memory controller code.
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*
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* If an imprecise data rate is too high due to rounding error
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* propagation, compute a suitably rounded mclk_ps to compute
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* a working memory controller configuration.
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*/
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unsigned int get_memory_clk_period_ps(void)
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{
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unsigned int mclk_ps;
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mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate();
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/* round to nearest 10 ps */
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return 10 * ((mclk_ps + 5) / 10);
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}
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/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
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unsigned int picos_to_mclk(unsigned int picos)
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{
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const unsigned long long ULL_2e12 = 2000000000000ULL;
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const unsigned long long ULL_8Fs = 0xFFFFFFFFULL;
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unsigned long long clks;
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unsigned long long clks_temp;
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if (!picos)
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return 0;
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clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos;
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clks_temp = clks;
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clks = clks / ULL_2e12;
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if (clks_temp % ULL_2e12) {
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clks++;
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}
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if (clks > ULL_8Fs) {
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clks = ULL_8Fs;
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}
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return (unsigned int) clks;
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}
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unsigned int mclk_to_picos(unsigned int mclk)
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{
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return get_memory_clk_period_ps() * mclk;
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}
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void
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__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
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unsigned int memctl_interleaved,
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unsigned int ctrl_num)
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{
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unsigned long long base = memctl_common_params->base_address;
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unsigned long long size = memctl_common_params->total_mem;
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/*
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* If no DIMMs on this controller, do not proceed any further.
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*/
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if (!memctl_common_params->ndimms_present) {
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return;
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}
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#if !defined(CONFIG_PHYS_64BIT)
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if (base >= CONFIG_MAX_MEM_MAPPED)
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return;
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if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
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size = CONFIG_MAX_MEM_MAPPED - base;
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#endif
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if (ctrl_num == 0) {
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/*
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* Set up LAW for DDR controller 1 space.
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*/
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unsigned int lawbar1_target_id = memctl_interleaved
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? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
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if (set_ddr_laws(base, size, lawbar1_target_id) < 0) {
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printf("ERROR\n");
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return ;
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}
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} else if (ctrl_num == 1) {
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if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) {
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printf("ERROR\n");
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return ;
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}
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} else {
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printf("unexpected controller number %u in %s\n",
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ctrl_num, __FUNCTION__);
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}
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}
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__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
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fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
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unsigned int memctl_interleaved,
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unsigned int ctrl_num);
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