Simon Glass 90b16d1491 x86: chromebook_link: dts: Add PCH and LPC devices ... The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>		2015-04-18 11:11:15 -06:00
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baytrail	x86: Add a x86_ prefix to the x86-specific PCI functions	2015-04-16 19:27:41 -06:00
coreboot	dm: x86: pci: Convert coreboot to use driver model for pci	2015-04-18 11:11:09 -06:00
ivybridge	x86: chromebook_link: dts: Add PCH and LPC devices	2015-04-18 11:11:15 -06:00
quark	x86: Add a x86_ prefix to the x86-specific PCI functions	2015-04-16 19:27:41 -06:00
queensbay	x86: Add a x86_ prefix to the x86-specific PCI functions	2015-04-16 19:27:41 -06:00
call64.S	x86: Add support for starting 64-bit kernel	2014-10-28 20:43:47 -06:00
config.mk	x86: Factor out common values in the link script	2014-11-25 06:33:59 -07:00
cpu.c	x86: Save mtrr support flag in global data	2015-01-23 17:24:55 -07:00
interrupts.c	x86: Drop old CONFIG_INTEL_CORE_ARCH code	2014-11-25 06:34:03 -07:00
lapic.c	x86: Add LAPIC setup code	2014-11-25 06:34:11 -07:00
Makefile	x86: Enable the Intel quark/galileo build	2015-02-06 12:07:42 -07:00
mtrr.c	x86: Test mtrr support flag before accessing mtrr msr	2015-01-23 17:24:55 -07:00
pci.c	dm: x86: pci: Add a PCI driver for driver model	2015-04-18 11:11:09 -06:00
resetvec.S	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
start16.S	x86: Fix various code format issues in start16.S	2015-01-23 17:24:55 -07:00
start.S	remove unnecessary version.h includes	2015-03-24 10:50:50 -04:00
turbo.c	x86: Add Intel speedstep and turbo mode code	2014-11-25 06:34:02 -07:00
u-boot.lds	x86: Factor out common values in the link script	2014-11-25 06:33:59 -07:00