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![]() qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYDUezQAKCRDKSWXLKUoM IbtgAJ9jZ+BOtwFaHR19TENC2DsHTINnnwCfSDn3fU0OFJRI0HD7pRxXr4xrb3M= =Kr8x -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name |
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.. | ||
armada-37xx-wdt.c | ||
ast2600_wdt.c | ||
ast_wdt.c | ||
at91sam9_wdt.c | ||
bcm6345_wdt.c | ||
cdns_wdt.c | ||
cortina_wdt.c | ||
designware_wdt.c | ||
ftwdt010_wdt.c | ||
imx_watchdog.c | ||
Kconfig | ||
Makefile | ||
mpc8xx_wdt.c | ||
mt7620_wdt.c | ||
mt7621_wdt.c | ||
mtk_wdt.c | ||
octeontx_wdt.c | ||
omap_wdt.c | ||
orion_wdt.c | ||
rti_wdt.c | ||
s5p_wdt.c | ||
sandbox_wdt.c | ||
sbsa_gwdt.c | ||
sp805_wdt.c | ||
stm32mp_wdt.c | ||
tangier_wdt.c | ||
ulp_wdog.c | ||
wdt-uclass.c | ||
xilinx_tb_wdt.c | ||
xilinx_wwdt.c |