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https://github.com/brain-hackers/u-boot-brain
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8564acf936
- Correct flash and JFFS2 support for MPC8260ADS - fix PVR values and clock generation for PowerQUICC II family (8270/8275/8280) * Patch by Bernhard Kuhn, 08 Jul 2003: - add support for M68K targets * Patch by Ken Chou, 3 Jul: - Fix PCI config table for A3000 - Fix iobase for natsemi.c (PCI_BASE_ADDRESS_0 is the IO base register for DP83815) * Allow to enable "slow" POST routines by key press on power-on * Fix temperature dependend switching of LCD backlight on LWMON * Tweak output format for LWMON |
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a3000.c | ||
config.mk | ||
flash.c | ||
Makefile | ||
README | ||
u-boot.lds |
U-Boot for Artis SBC-A3000 --------------------------- Artis SBC-A3000 has one flash socket that the user uses Intel 28F128J3A (16MB) or 28F064J3A (8MB) chips. In board's notation, bank 0 is the one at the address of 0xFF000000. bank 1 is the one at the address of 0xFF800000 On power-up the processor jumps to the address of 0xFFF00100, the last megabyte of the bank 0 of flash. Thus, U-Boot is configured to reside in flash starting at the address of 0xFFF00000. The environment space is located in flash separately from U-Boot, at the address of 0xFFFE0000. There is a National ns83815 10/100M ethernet controller on-board.