David Wu 2e4ce50d1a rockchip: clk: Add rv1108 SARADC clock support ... The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>		2017-10-01 00:33:29 +02:00
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clk_rk322x.c	rockchip: clk: remove RATE_TO_DIV	2017-08-13 17:15:09 +02:00
clk_rk3036.c	rockchip: clk: remove RATE_TO_DIV	2017-08-13 17:15:09 +02:00
clk_rk3188.c	rockchip: clk: remove RATE_TO_DIV	2017-08-13 17:15:09 +02:00
clk_rk3288.c	rockchip: clk: remove RATE_TO_DIV	2017-08-13 17:15:09 +02:00
clk_rk3328.c	rockchip: clk: update dwmmc clock div	2017-08-13 17:15:09 +02:00
clk_rk3368.c	rockchip: clk: rk3368: Convert to livetree	2017-09-18 20:40:34 +02:00
clk_rk3399.c	rockchip: clk: rk3399: Convert to livetree	2017-09-18 20:40:37 +02:00
clk_rv1108.c	rockchip: clk: Add rv1108 SARADC clock support	2017-10-01 00:33:29 +02:00
Makefile	rockchip: rk322x: add clock driver	2017-07-11 12:13:45 +02:00