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![Stefan Roese](/assets/img/avatar_default.png)
gcc 5.1 generates this new warning (for Armada 38x platforms): drivers/ddr/marvell/a38x/ddr3_debug.c: In function 'hws_ddr3_tip_read_training_result': drivers/ddr/marvell/a38x/ddr3_debug.c:177:40: warning: 'sizeof' on array function parameter 'result' will return size of 'enum hws_result (*)[1]' [-Wsizeof-array-argument] memcpy(result, training_result, sizeof(result)); ^ drivers/ddr/marvell/a38x/ddr3_debug.c:171:31: note: declared here u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]) ^ Since this functions is not referenced anywhere, lets just remove it. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
179 lines
4.4 KiB
C
179 lines
4.4 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_TRAINING_IP_H_
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#define _DDR3_TRAINING_IP_H_
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#include "ddr3_training_ip_def.h"
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#include "ddr_topology_def.h"
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#include "ddr_training_ip_db.h"
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#define DDR3_TIP_VERSION_STRING "DDR3 Training Sequence - Ver TIP-1.29."
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#define MAX_CS_NUM 4
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#define MAX_TOTAL_BUS_NUM (MAX_INTERFACE_NUM * MAX_BUS_NUM)
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#define MAX_DQ_NUM 40
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#define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2)
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#define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1)
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#define INIT_CONTROLLER_MASK_BIT 0x00000001
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#define STATIC_LEVELING_MASK_BIT 0x00000002
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#define SET_LOW_FREQ_MASK_BIT 0x00000004
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#define LOAD_PATTERN_MASK_BIT 0x00000008
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#define SET_MEDIUM_FREQ_MASK_BIT 0x00000010
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#define WRITE_LEVELING_MASK_BIT 0x00000020
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#define LOAD_PATTERN_2_MASK_BIT 0x00000040
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#define READ_LEVELING_MASK_BIT 0x00000080
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#define SW_READ_LEVELING_MASK_BIT 0x00000100
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#define WRITE_LEVELING_SUPP_MASK_BIT 0x00000200
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#define PBS_RX_MASK_BIT 0x00000400
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#define PBS_TX_MASK_BIT 0x00000800
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#define SET_TARGET_FREQ_MASK_BIT 0x00001000
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#define ADJUST_DQS_MASK_BIT 0x00002000
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#define WRITE_LEVELING_TF_MASK_BIT 0x00004000
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#define LOAD_PATTERN_HIGH_MASK_BIT 0x00008000
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#define READ_LEVELING_TF_MASK_BIT 0x00010000
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#define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000
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#define DM_PBS_TX_MASK_BIT 0x00040000
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#define CENTRALIZATION_RX_MASK_BIT 0x00100000
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#define CENTRALIZATION_TX_MASK_BIT 0x00200000
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#define TX_EMPHASIS_MASK_BIT 0x00400000
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#define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000
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#define VREF_CALIBRATION_MASK_BIT 0x01000000
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enum hws_result {
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TEST_FAILED = 0,
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TEST_SUCCESS = 1,
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NO_TEST_DONE = 2
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};
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enum hws_training_result {
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RESULT_PER_BIT,
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RESULT_PER_BYTE
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};
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enum auto_tune_stage {
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INIT_CONTROLLER,
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STATIC_LEVELING,
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SET_LOW_FREQ,
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LOAD_PATTERN,
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SET_MEDIUM_FREQ,
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WRITE_LEVELING,
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LOAD_PATTERN_2,
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READ_LEVELING,
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WRITE_LEVELING_SUPP,
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PBS_RX,
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PBS_TX,
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SET_TARGET_FREQ,
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ADJUST_DQS,
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WRITE_LEVELING_TF,
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READ_LEVELING_TF,
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WRITE_LEVELING_SUPP_TF,
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DM_PBS_TX,
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VREF_CALIBRATION,
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CENTRALIZATION_RX,
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CENTRALIZATION_TX,
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TX_EMPHASIS,
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LOAD_PATTERN_HIGH,
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PER_BIT_READ_LEVELING_TF,
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MAX_STAGE_LIMIT
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};
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enum hws_access_type {
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ACCESS_TYPE_UNICAST = 0,
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ACCESS_TYPE_MULTICAST = 1
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};
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enum hws_algo_type {
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ALGO_TYPE_DYNAMIC,
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ALGO_TYPE_STATIC
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};
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struct init_cntr_param {
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int is_ctrl64_bit;
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int do_mrs_phy;
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int init_phy;
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int msys_init;
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};
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struct pattern_info {
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u8 num_of_phases_tx;
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u8 tx_burst_size;
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u8 delay_between_bursts;
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u8 num_of_phases_rx;
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u32 start_addr;
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u8 pattern_len;
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};
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/* CL value for each frequency */
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struct cl_val_per_freq {
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u8 cl_val[DDR_FREQ_LIMIT];
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};
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struct cs_element {
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u8 cs_num;
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u8 num_of_cs;
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};
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struct mode_info {
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/* 32 bits representing MRS bits */
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u32 reg_mr0[MAX_INTERFACE_NUM];
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u32 reg_mr1[MAX_INTERFACE_NUM];
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u32 reg_mr2[MAX_INTERFACE_NUM];
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u32 reg_m_r3[MAX_INTERFACE_NUM];
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/*
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* Each element in array represent read_data_sample register delay for
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* a specific interface.
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* Each register, 4 bits[0+CS*8 to 4+CS*8] represent Number of DDR
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* cycles from read command until data is ready to be fetched from
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* the PHY, when accessing CS.
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*/
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u32 read_data_sample[MAX_INTERFACE_NUM];
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/*
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* Each element in array represent read_data_sample register delay for
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* a specific interface.
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* Each register, 4 bits[0+CS*8 to 4+CS*8] represent the total delay
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* from read command until opening the read mask, when accessing CS.
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* This field defines the delay in DDR cycles granularity.
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*/
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u32 read_data_ready[MAX_INTERFACE_NUM];
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};
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struct hws_tip_freq_config_info {
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u8 is_supported;
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u8 bw_per_freq;
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u8 rate_per_freq;
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};
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struct hws_cs_config_info {
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u32 cs_reg_value;
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u32 cs_cbe_value;
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};
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struct dfx_access {
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u8 pipe;
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u8 client;
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};
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struct hws_xsb_info {
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struct dfx_access *dfx_table;
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};
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int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
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int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
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int hws_ddr3_tip_init_controller(u32 dev_num,
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struct init_cntr_param *init_cntr_prm);
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int hws_ddr3_tip_load_topology_map(u32 dev_num,
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struct hws_topology_map *topology);
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int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
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int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
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int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
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u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
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u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
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#endif /* _DDR3_TRAINING_IP_H_ */
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