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https://github.com/brain-hackers/u-boot-brain
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66ebea06f7
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, the rsb is also used to communicate with the pmic on the A80, and is documented in the A80 user manual. This commit adds support for this based on the rsb driver from the allwinner u-boot sources. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
56 lines
1.4 KiB
C
56 lines
1.4 KiB
C
/*
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* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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*
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* Based on allwinner u-boot sources rsb code which is:
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* (C) Copyright 2007-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* lixiang <lixiang@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __SUNXI_RSB_H
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#define __SUNXI_RSB_H
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#include <common.h>
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#include <asm/io.h>
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struct sunxi_rsb_reg {
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u32 ctrl; /* 0x00 */
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u32 ccr; /* 0x04 */
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u32 inte; /* 0x08 */
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u32 stat; /* 0x0c */
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u32 addr; /* 0x10 */
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u8 res0[8]; /* 0x14 */
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u32 data; /* 0x1c */
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u8 res1[4]; /* 0x20 */
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u32 lcr; /* 0x24 */
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u32 dmcr; /* 0x28 */
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u32 cmd; /* 0x2c */
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u32 devaddr; /* 0x30 */
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};
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#define RSB_CTRL_SOFT_RST (1 << 0)
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#define RSB_CTRL_START_TRANS (1 << 7)
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#define RSB_STAT_TOVER_INT (1 << 0)
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#define RSB_STAT_TERR_INT (1 << 1)
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#define RSB_STAT_LBSY_INT (1 << 2)
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#define RSB_DMCR_DEVICE_MODE_START (1 << 31)
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#define RSB_CMD_BYTE_WRITE 0x4e
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#define RSB_CMD_BYTE_READ 0x8b
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#define RSB_CMD_SET_RTSADDR 0xe8
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#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16)
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#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0)
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void rsb_init(void);
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int rsb_set_device_mode(u32 device_mode_data);
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int rsb_set_device_address(u16 device_addr, u16 runtime_addr);
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int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data);
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int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data);
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#endif
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