mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
2dc63f7367
The intention of the removal is the preparation to introduce the new AT91 PIO pinctrl driver. Use the union to make the PIO3 and PIO2's registers be together and make their offset aligned. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
588 lines
13 KiB
C
588 lines
13 KiB
C
/*
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* Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
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*
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* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
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*
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* Copyright (C) 2005 HP Labs
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <asm/gpio.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pio.h>
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#define GPIO_PER_BANK 32
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static struct at91_port *at91_pio_get_port(unsigned port)
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{
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switch (port) {
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case AT91_PIO_PORTA:
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return (struct at91_port *)ATMEL_BASE_PIOA;
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case AT91_PIO_PORTB:
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return (struct at91_port *)ATMEL_BASE_PIOB;
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case AT91_PIO_PORTC:
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return (struct at91_port *)ATMEL_BASE_PIOC;
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#if (ATMEL_PIO_PORTS > 3)
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case AT91_PIO_PORTD:
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return (struct at91_port *)ATMEL_BASE_PIOD;
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#if (ATMEL_PIO_PORTS > 4)
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case AT91_PIO_PORTE:
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return (struct at91_port *)ATMEL_BASE_PIOE;
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#endif
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#endif
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default:
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printf("Error: at91_gpio: Fail to get PIO base!\n");
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return NULL;
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}
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}
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static void at91_set_port_pullup(struct at91_port *at91_port, unsigned offset,
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int use_pullup)
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{
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u32 mask;
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mask = 1 << offset;
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if (use_pullup)
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writel(mask, &at91_port->puer);
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else
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writel(mask, &at91_port->pudr);
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writel(mask, &at91_port->per);
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}
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int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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if (at91_port && (pin < GPIO_PER_BANK))
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at91_set_port_pullup(at91_port, pin, use_pullup);
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return 0;
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}
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/*
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* mux the pin to the "GPIO" peripheral role.
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*/
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int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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writel(mask, &at91_port->idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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writel(mask, &at91_port->per);
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}
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return 0;
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}
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/*
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* mux the pin to the "A" internal peripheral role.
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*/
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int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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writel(mask, &at91_port->idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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writel(mask, &at91_port->mux.pio2.asr);
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writel(mask, &at91_port->pdr);
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}
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return 0;
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}
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/*
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* mux the pin to the "B" internal peripheral role.
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*/
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int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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writel(mask, &at91_port->idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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writel(mask, &at91_port->mux.pio2.bsr);
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writel(mask, &at91_port->pdr);
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}
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return 0;
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}
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/*
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* mux the pin to the "A" internal peripheral role.
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*/
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int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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writel(mask, &at91_port->idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
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&at91_port->mux.pio3.abcdsr1);
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writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
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&at91_port->mux.pio3.abcdsr2);
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writel(mask, &at91_port->pdr);
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}
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return 0;
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}
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/*
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* mux the pin to the "B" internal peripheral role.
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*/
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int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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writel(mask, &at91_port->idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
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&at91_port->mux.pio3.abcdsr1);
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writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
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&at91_port->mux.pio3.abcdsr2);
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writel(mask, &at91_port->pdr);
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}
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return 0;
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}
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/*
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* mux the pin to the "C" internal peripheral role.
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*/
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int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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writel(mask, &at91_port->idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
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&at91_port->mux.pio3.abcdsr1);
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writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
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&at91_port->mux.pio3.abcdsr2);
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writel(mask, &at91_port->pdr);
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}
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return 0;
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}
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/*
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* mux the pin to the "D" internal peripheral role.
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*/
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int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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writel(mask, &at91_port->idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
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&at91_port->mux.pio3.abcdsr1);
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writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
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&at91_port->mux.pio3.abcdsr2);
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writel(mask, &at91_port->pdr);
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}
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return 0;
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}
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#ifdef CONFIG_DM_GPIO
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static bool at91_get_port_output(struct at91_port *at91_port, int offset)
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{
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u32 mask, val;
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mask = 1 << offset;
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val = readl(&at91_port->osr);
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return val & mask;
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}
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#endif
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static void at91_set_port_input(struct at91_port *at91_port, int offset,
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int use_pullup)
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{
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u32 mask;
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mask = 1 << offset;
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writel(mask, &at91_port->idr);
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at91_set_port_pullup(at91_port, offset, use_pullup);
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writel(mask, &at91_port->odr);
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writel(mask, &at91_port->per);
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}
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
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* configure it for an input.
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*/
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int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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if (at91_port && (pin < GPIO_PER_BANK))
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at91_set_port_input(at91_port, pin, use_pullup);
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return 0;
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}
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static void at91_set_port_output(struct at91_port *at91_port, int offset,
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int value)
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{
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u32 mask;
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mask = 1 << offset;
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writel(mask, &at91_port->idr);
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writel(mask, &at91_port->pudr);
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if (value)
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writel(mask, &at91_port->sodr);
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else
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writel(mask, &at91_port->codr);
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writel(mask, &at91_port->oer);
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writel(mask, &at91_port->per);
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}
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
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* and configure it for an output.
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*/
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int at91_set_pio_output(unsigned port, u32 pin, int value)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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if (at91_port && (pin < GPIO_PER_BANK))
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at91_set_port_output(at91_port, pin, value);
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return 0;
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}
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/*
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* enable/disable the glitch filter. mostly used with IRQ handling.
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*/
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int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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if (is_on)
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writel(mask, &at91_port->ifer);
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else
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writel(mask, &at91_port->ifdr);
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}
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return 0;
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}
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/*
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* enable/disable the glitch filter. mostly used with IRQ handling.
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*/
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int at91_pio3_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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if (is_on) {
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writel(mask, &at91_port->mux.pio3.ifscdr);
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writel(mask, &at91_port->ifer);
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} else {
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writel(mask, &at91_port->ifdr);
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}
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}
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return 0;
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}
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/*
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* enable/disable the debounce filter.
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*/
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int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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if (is_on) {
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writel(mask, &at91_port->mux.pio3.ifscer);
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writel(div & PIO_SCDR_DIV, &at91_port->mux.pio3.scdr);
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writel(mask, &at91_port->ifer);
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} else {
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writel(mask, &at91_port->ifdr);
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}
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}
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return 0;
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}
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/*
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* enable/disable the pull-down.
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* If pull-up already enabled while calling the function, we disable it.
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*/
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int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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if (is_on) {
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at91_set_pio_pullup(port, pin, 0);
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writel(mask, &at91_port->mux.pio3.ppder);
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} else
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writel(mask, &at91_port->mux.pio3.ppddr);
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}
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return 0;
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}
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int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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if (use_pullup)
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at91_pio3_set_pio_pulldown(port, pin, 0);
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if (at91_port && (pin < GPIO_PER_BANK))
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at91_set_port_pullup(at91_port, pin, use_pullup);
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return 0;
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}
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/*
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* disable Schmitt trigger
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*/
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int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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writel(readl(&at91_port->schmitt) | mask,
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&at91_port->schmitt);
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}
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return 0;
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}
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/*
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* enable/disable the multi-driver. This is only valid for output and
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* allows the output pin to run as an open collector output.
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*/
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int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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u32 mask;
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if (at91_port && (pin < GPIO_PER_BANK)) {
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mask = 1 << pin;
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if (is_on)
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writel(mask, &at91_port->mder);
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else
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writel(mask, &at91_port->mddr);
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}
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return 0;
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}
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static void at91_set_port_value(struct at91_port *at91_port, int offset,
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int value)
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{
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u32 mask;
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mask = 1 << offset;
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if (value)
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writel(mask, &at91_port->sodr);
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else
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writel(mask, &at91_port->codr);
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}
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/*
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* assuming the pin is muxed as a gpio output, set its value.
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*/
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int at91_set_pio_value(unsigned port, unsigned pin, int value)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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if (at91_port && (pin < GPIO_PER_BANK))
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at91_set_port_value(at91_port, pin, value);
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return 0;
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}
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static int at91_get_port_value(struct at91_port *at91_port, int offset)
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{
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u32 pdsr = 0, mask;
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mask = 1 << offset;
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pdsr = readl(&at91_port->pdsr) & mask;
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return pdsr != 0;
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}
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/*
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* read the pin's value (works even if it's not muxed as a gpio).
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*/
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int at91_get_pio_value(unsigned port, unsigned pin)
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{
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struct at91_port *at91_port = at91_pio_get_port(port);
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if (at91_port && (pin < GPIO_PER_BANK))
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return at91_get_port_value(at91_port, pin);
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return 0;
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}
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#ifndef CONFIG_DM_GPIO
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/* Common GPIO API */
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int gpio_request(unsigned gpio, const char *label)
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{
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return 0;
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}
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int gpio_free(unsigned gpio)
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{
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return 0;
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}
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int gpio_direction_input(unsigned gpio)
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{
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at91_set_pio_input(at91_gpio_to_port(gpio),
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at91_gpio_to_pin(gpio), 0);
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return 0;
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}
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int gpio_direction_output(unsigned gpio, int value)
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{
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at91_set_pio_output(at91_gpio_to_port(gpio),
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at91_gpio_to_pin(gpio), value);
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return 0;
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}
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int gpio_get_value(unsigned gpio)
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{
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return at91_get_pio_value(at91_gpio_to_port(gpio),
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at91_gpio_to_pin(gpio));
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}
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int gpio_set_value(unsigned gpio, int value)
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{
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at91_set_pio_value(at91_gpio_to_port(gpio),
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at91_gpio_to_pin(gpio), value);
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return 0;
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}
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#endif
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#ifdef CONFIG_DM_GPIO
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struct at91_port_priv {
|
|
struct at91_port *regs;
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|
};
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|
|
|
/* set GPIO pin 'gpio' as an input */
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|
static int at91_gpio_direction_input(struct udevice *dev, unsigned offset)
|
|
{
|
|
struct at91_port_priv *port = dev_get_priv(dev);
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|
|
|
at91_set_port_input(port->regs, offset, 0);
|
|
|
|
return 0;
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|
}
|
|
|
|
/* set GPIO pin 'gpio' as an output, with polarity 'value' */
|
|
static int at91_gpio_direction_output(struct udevice *dev, unsigned offset,
|
|
int value)
|
|
{
|
|
struct at91_port_priv *port = dev_get_priv(dev);
|
|
|
|
at91_set_port_output(port->regs, offset, value);
|
|
|
|
return 0;
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|
}
|
|
|
|
/* read GPIO IN value of pin 'gpio' */
|
|
static int at91_gpio_get_value(struct udevice *dev, unsigned offset)
|
|
{
|
|
struct at91_port_priv *port = dev_get_priv(dev);
|
|
|
|
return at91_get_port_value(port->regs, offset);
|
|
}
|
|
|
|
/* write GPIO OUT value to pin 'gpio' */
|
|
static int at91_gpio_set_value(struct udevice *dev, unsigned offset,
|
|
int value)
|
|
{
|
|
struct at91_port_priv *port = dev_get_priv(dev);
|
|
|
|
at91_set_port_value(port->regs, offset, value);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int at91_gpio_get_function(struct udevice *dev, unsigned offset)
|
|
{
|
|
struct at91_port_priv *port = dev_get_priv(dev);
|
|
|
|
/* GPIOF_FUNC is not implemented yet */
|
|
if (at91_get_port_output(port->regs, offset))
|
|
return GPIOF_OUTPUT;
|
|
else
|
|
return GPIOF_INPUT;
|
|
}
|
|
|
|
static const struct dm_gpio_ops gpio_at91_ops = {
|
|
.direction_input = at91_gpio_direction_input,
|
|
.direction_output = at91_gpio_direction_output,
|
|
.get_value = at91_gpio_get_value,
|
|
.set_value = at91_gpio_set_value,
|
|
.get_function = at91_gpio_get_function,
|
|
};
|
|
|
|
static int at91_gpio_probe(struct udevice *dev)
|
|
{
|
|
struct at91_port_priv *port = dev_get_priv(dev);
|
|
struct at91_port_platdata *plat = dev_get_platdata(dev);
|
|
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
|
|
|
|
uc_priv->bank_name = plat->bank_name;
|
|
uc_priv->gpio_count = GPIO_PER_BANK;
|
|
port->regs = (struct at91_port *)plat->base_addr;
|
|
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_DRIVER(gpio_at91) = {
|
|
.name = "gpio_at91",
|
|
.id = UCLASS_GPIO,
|
|
.ops = &gpio_at91_ops,
|
|
.probe = at91_gpio_probe,
|
|
.priv_auto_alloc_size = sizeof(struct at91_port_priv),
|
|
};
|
|
#endif
|