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https://github.com/brain-hackers/u-boot-brain
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2dbba24088
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions. This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX This improves readability, no functional change. Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
62 lines
909 B
Plaintext
62 lines
909 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*/
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#include "cn9130-crb.dtsi"
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/ {
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model = "CN9130-CRB-B";
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compatible = "marvell,cn9130-crb-B",
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"marvell,cn9130",
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"marvell,armada-ap806-quad",
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"marvell,armada-ap806";
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};
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&cp0_comphy {
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phy0 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_USB3_HOST0>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_SATA0>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_USB3_HOST1>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_SFI>;
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phy-speed = <COMPHY_SPEED_10_3125G>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_SGMII2>;
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phy-speed = <COMPHY_SPEED_3_125G>;
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};
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};
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&cp0_sata0 {
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status = "okay";
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};
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&cp0_pcie0 {
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num-lanes = <1>;
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/* non-prefetchable memory */
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ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
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status = "disabled";
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};
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&cp0_usb3_0 {
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status = "okay";
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};
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&cp0_usb3_1 {
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status = "okay";
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};
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