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https://github.com/brain-hackers/u-boot-brain
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![Dirk Eibach](/assets/img/avatar_default.png)
A set of accessor functions was added to be able to access not only memory mapped FPGA in a generic way. Thanks to Wolfgang Denk for getting this sorted properly. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
304 lines
5.4 KiB
C
304 lines
5.4 KiB
C
/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#include <dtt.h>
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#include "405ep.h"
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#include <gdsys_fpga.h>
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#include "../common/osd.h"
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#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
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#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
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#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
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#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
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#define LATCH2_MC2_PRESENT_N 0x0080
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enum {
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UNITTYPE_VIDEO_USER = 0,
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UNITTYPE_MAIN_USER = 1,
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UNITTYPE_VIDEO_SERVER = 2,
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UNITTYPE_MAIN_SERVER = 3,
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};
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enum {
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HWVER_101 = 0,
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HWVER_110 = 1,
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HWVER_120 = 2,
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HWVER_130 = 3,
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};
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enum {
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AUDIO_NONE = 0,
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AUDIO_TX = 1,
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AUDIO_RX = 2,
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AUDIO_RXTX = 3,
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};
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enum {
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SYSCLK_156250 = 2,
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};
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enum {
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RAM_NONE = 0,
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RAM_DDR2_32 = 1,
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RAM_DDR2_64 = 2,
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};
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struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
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int misc_init_r(void)
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{
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/* startup fans */
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dtt_init();
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return 0;
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}
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static unsigned int get_hwver(void)
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{
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u16 latch3 = in_le16((void *)LATCH3_BASE);
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return latch3 & 0x0003;
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}
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static unsigned int get_mc2_present(void)
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{
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u16 latch2 = in_le16((void *)LATCH2_BASE);
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return !(latch2 & LATCH2_MC2_PRESENT_N);
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}
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static void print_fpga_info(unsigned dev)
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{
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u16 versions;
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u16 fpga_version;
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u16 fpga_features;
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unsigned unit_type;
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unsigned hardware_version;
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unsigned feature_rs232;
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unsigned feature_audio;
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unsigned feature_sysclock;
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unsigned feature_ramconfig;
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unsigned feature_carrier_speed;
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unsigned feature_carriers;
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unsigned feature_video_channels;
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int fpga_state = get_fpga_state(dev);
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printf("FPGA%d: ", dev);
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FPGA_GET_REG(dev, versions, &versions);
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FPGA_GET_REG(dev, fpga_version, &fpga_version);
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FPGA_GET_REG(dev, fpga_features, &fpga_features);
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hardware_version = versions & 0x000f;
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if (fpga_state
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&& !((hardware_version == HWVER_101)
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&& (fpga_state == FPGA_STATE_DONE_FAILED))) {
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puts("not available\n");
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print_fpga_state(dev);
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return;
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}
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unit_type = (versions >> 4) & 0x000f;
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hardware_version = versions & 0x000f;
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feature_rs232 = fpga_features & (1<<11);
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feature_audio = (fpga_features >> 9) & 0x0003;
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feature_sysclock = (fpga_features >> 7) & 0x0003;
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feature_ramconfig = (fpga_features >> 5) & 0x0003;
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feature_carrier_speed = fpga_features & (1<<4);
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feature_carriers = (fpga_features >> 2) & 0x0003;
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feature_video_channels = fpga_features & 0x0003;
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switch (unit_type) {
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case UNITTYPE_VIDEO_USER:
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printf("Videochannel Userside");
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break;
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case UNITTYPE_MAIN_USER:
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printf("Mainchannel Userside");
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break;
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case UNITTYPE_VIDEO_SERVER:
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printf("Videochannel Serverside");
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break;
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case UNITTYPE_MAIN_SERVER:
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printf("Mainchannel Serverside");
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break;
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default:
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printf("UnitType %d(not supported)", unit_type);
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break;
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}
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switch (hardware_version) {
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case HWVER_101:
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printf(" HW-Ver 1.01\n");
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break;
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case HWVER_110:
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printf(" HW-Ver 1.10-1.12\n");
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break;
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case HWVER_120:
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printf(" HW-Ver 1.20\n");
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break;
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case HWVER_130:
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printf(" HW-Ver 1.30\n");
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break;
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default:
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printf(" HW-Ver %d(not supported)\n",
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hardware_version);
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break;
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}
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printf(" FPGA V %d.%02d, features:",
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fpga_version / 100, fpga_version % 100);
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printf(" %sRS232", feature_rs232 ? "" : "no ");
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switch (feature_audio) {
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case AUDIO_NONE:
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printf(", no audio");
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break;
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case AUDIO_TX:
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printf(", audio tx");
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break;
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case AUDIO_RX:
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printf(", audio rx");
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break;
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case AUDIO_RXTX:
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printf(", audio rx+tx");
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break;
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default:
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printf(", audio %d(not supported)", feature_audio);
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break;
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}
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switch (feature_sysclock) {
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case SYSCLK_156250:
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printf(", clock 156.25 MHz");
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break;
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default:
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printf(", clock %d(not supported)", feature_sysclock);
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break;
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}
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puts(",\n ");
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switch (feature_ramconfig) {
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case RAM_NONE:
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printf("no RAM");
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break;
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case RAM_DDR2_32:
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printf("RAM 32 bit DDR2");
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break;
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case RAM_DDR2_64:
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printf("RAM 64 bit DDR2");
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break;
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default:
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printf("RAM %d(not supported)", feature_ramconfig);
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break;
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}
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printf(", %d carrier(s) %s", feature_carriers,
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feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
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printf(", %d video channel(s)\n", feature_video_channels);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char *s = getenv("serial#");
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puts("Board: ");
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puts("DLVision 10G");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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puts("\n");
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return 0;
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}
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int last_stage_init(void)
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{
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u16 versions;
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FPGA_GET_REG(0, versions, &versions);
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print_fpga_info(0);
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if (get_mc2_present())
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print_fpga_info(1);
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if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
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return 0;
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if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
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osd_probe(0);
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if (get_mc2_present() &&
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(!get_fpga_state(1) || (get_hwver() == HWVER_101)))
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osd_probe(1);
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return 0;
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}
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void gd405ep_init(void)
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{
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}
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void gd405ep_set_fpga_reset(unsigned state)
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{
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if (state) {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
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} else {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
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}
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}
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void gd405ep_setup_hw(void)
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{
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/*
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* set "startup-finished"-gpios
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*/
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gpio_write_bit(21, 0);
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gpio_write_bit(22, 1);
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}
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int gd405ep_get_fpga_done(unsigned fpga)
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{
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return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
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}
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