mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 03:19:43 +09:00
2d9925bce3
When only sdhci1 IP is enabled and SD_MODE1 bootmode is selected U-Boot using sdboot1 variable which refers to mmc dev 1. But this device doesn't exist because only one controller is available. This patch fix logic around sdboot mode with using sdbootdev internal variable. Reported-by: Chris Kohn <ckohn@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
154 lines
2.9 KiB
C
154 lines
2.9 KiB
C
/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <usb.h>
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#include <dwc3-uboot.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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printf("EL Level:\tEL%d\n", current_el());
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return 0;
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}
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int board_early_init_r(void)
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{
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u32 val;
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if (current_el() == 3) {
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
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writel(val, &crlapb_base->timestamp_ref_ctrl);
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/* Program freq register in System counter */
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writel(zynqmp_get_system_timer_freq(),
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&iou_scntr_secure->base_frequency_id_register);
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/* And enable system counter */
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writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
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&iou_scntr_secure->counter_control_register);
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}
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/* Program freq register in System counter and enable system counter */
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writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
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writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
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ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
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&iou_scntr->counter_control_register);
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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int timer_init(void)
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{
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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}
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#ifdef CONFIG_SCSI_AHCI_PLAT
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void scsi_init(void)
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{
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ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
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scsi_scan(1);
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}
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#endif
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int board_late_init(void)
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{
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u32 reg = 0;
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u8 bootmode;
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reg = readl(&crlapb_base->boot_mode);
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bootmode = reg & BOOT_MODES_MASK;
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puts("Bootmode: ");
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switch (bootmode) {
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case JTAG_MODE:
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puts("JTAG_MODE\n");
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setenv("modeboot", "jtagboot");
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break;
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case QSPI_MODE_24BIT:
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case QSPI_MODE_32BIT:
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setenv("modeboot", "qspiboot");
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puts("QSPI_MODE\n");
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break;
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case EMMC_MODE:
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puts("EMMC_MODE\n");
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setenv("modeboot", "sdboot");
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break;
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case SD_MODE:
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puts("SD_MODE\n");
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setenv("modeboot", "sdboot");
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break;
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case SD_MODE1:
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puts("SD_MODE1\n");
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#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
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setenv("sdbootdev", "1");
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#endif
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setenv("modeboot", "sdboot");
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break;
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case NAND_MODE:
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puts("NAND_MODE\n");
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setenv("modeboot", "nandboot");
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break;
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default:
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printf("Invalid Boot Mode:0x%x\n", bootmode);
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break;
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}
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return 0;
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}
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int checkboard(void)
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{
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puts("Board:\tXilinx ZynqMP\n");
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return 0;
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}
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#ifdef CONFIG_USB_DWC3
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static struct dwc3_device dwc3_device_data = {
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.maximum_speed = USB_SPEED_HIGH,
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.base = ZYNQMP_USB0_XHCI_BASEADDR,
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.dr_mode = USB_DR_MODE_PERIPHERAL,
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.index = 0,
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};
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int usb_gadget_handle_interrupts(void)
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{
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dwc3_uboot_handle_interrupt(0);
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return 0;
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}
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int board_usb_init(int index, enum usb_init_type init)
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{
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return dwc3_uboot_init(&dwc3_device_data);
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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dwc3_uboot_exit(index);
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return 0;
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}
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#endif
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