mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 18:09:03 +09:00
![Tom Rix](/assets/img/avatar_default.png)
This problem is seen on Zoom1 and Zoom2 in the startup and when i2c probe is used Before : In: serial Out: serial Err: serial timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_pin: I2C_STAT=1000 I2C read: I/O error timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_bb: I2C_STAT=1000 Die ID #327c00020000000004013ddd05026013 Hit any key to stop autoboot: 0 OMAP3 Zoom1# i2c probe Valid chip addresses:timed out in wait_for_bb: I2C_STAT=1000 02 03 04 05 06 07 08 09 0A 0B 0C 0D <snip> After : In: serial Out: serial Err: serial Die ID #327c00020000000004013ddd05026013 Hit any key to stop autoboot: 0 OMAP3 Zoom1# i2c probe Valid chip addresses: 48 49 4A 4B The addresses are for the twl4030. The prescalar that converts the function clock to the sampling clock is hardcoded to 0. The reference manual recommends 7 if the function clock is 96MHz. Instead of just changing the hardcoded values, the prescalar is calculated from the value I2C_IP_CLK. The i2c #defines are in kHz. The speed passed into the i2c init routine is in Hz. To be consistent, change the defines to be in Hz. The timing calculations are based on what is done in the linux 2.6.30 kernel in drivers/i2c/buses/i2c_omap.c as apposed to what is done in TRM. The major variables in the timing caculations are specified as #defines that can be overriden as required. The variables and their defaults are I2C_IP_CLK SYSTEM_CLOCK_96 I2C_INTERNAL_SAMPLING_CLK 19200000 I2C_FASTSPEED_SCLL_TRIM 6 I2C_FASTSPEED_SCLH_TRIM 6 I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM I2C_HIGHSPEED_PHASE_TWO_SCLH I2C_FASTSPEED_SCLH_TRIM This was runtime verified on Zoom1, Zoom2, Beagle and Overo. The 400kHz and 3.4M cases were verifed on test Zoom1, Zoom2, Beagle and Overo configurations. Testing for omap2 will be done in a second step as Nishanth and Jean-Christophe commented. Signed-off-by: Tom Rix <Tom.Rix@windriver.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Heiko Schocher <hs@denx.de>
406 lines
9.1 KiB
C
406 lines
9.1 KiB
C
/*
|
|
* Basic I2C functions
|
|
*
|
|
* Copyright (c) 2004 Texas Instruments
|
|
*
|
|
* This package is free software; you can redistribute it and/or
|
|
* modify it under the terms of the license found in the file
|
|
* named COPYING that should have accompanied this file.
|
|
*
|
|
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
|
|
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
|
|
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
|
|
*
|
|
* Author: Jian Zhang jzhang@ti.com, Texas Instruments
|
|
*
|
|
* Copyright (c) 2003 Wolfgang Denk, wd@denx.de
|
|
* Rewritten to fit into the current U-Boot framework
|
|
*
|
|
* Adapted for OMAP2420 I2C, r-woodruff2@ti.com
|
|
*
|
|
*/
|
|
|
|
#include <common.h>
|
|
|
|
#include <asm/arch/i2c.h>
|
|
#include <asm/io.h>
|
|
|
|
static void wait_for_bb (void);
|
|
static u16 wait_for_pin (void);
|
|
static void flush_fifo(void);
|
|
|
|
void i2c_init (int speed, int slaveadd)
|
|
{
|
|
int psc, fsscll, fssclh;
|
|
int hsscll = 0, hssclh = 0;
|
|
u32 scll, sclh;
|
|
|
|
/* Only handle standard, fast and high speeds */
|
|
if ((speed != OMAP_I2C_STANDARD) &&
|
|
(speed != OMAP_I2C_FAST_MODE) &&
|
|
(speed != OMAP_I2C_HIGH_SPEED)) {
|
|
printf("Error : I2C unsupported speed %d\n", speed);
|
|
return;
|
|
}
|
|
|
|
psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
|
|
psc -= 1;
|
|
if (psc < I2C_PSC_MIN) {
|
|
printf("Error : I2C unsupported prescalar %d\n", psc);
|
|
return;
|
|
}
|
|
|
|
if (speed == OMAP_I2C_HIGH_SPEED) {
|
|
/* High speed */
|
|
|
|
/* For first phase of HS mode */
|
|
fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
|
|
(2 * OMAP_I2C_FAST_MODE);
|
|
|
|
fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
|
|
fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
|
|
if (((fsscll < 0) || (fssclh < 0)) ||
|
|
((fsscll > 255) || (fssclh > 255))) {
|
|
printf("Error : I2C initializing first phase clock\n");
|
|
return;
|
|
}
|
|
|
|
/* For second phase of HS mode */
|
|
hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
|
|
|
|
hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
|
|
hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
|
|
if (((fsscll < 0) || (fssclh < 0)) ||
|
|
((fsscll > 255) || (fssclh > 255))) {
|
|
printf("Error : I2C initializing second phase clock\n");
|
|
return;
|
|
}
|
|
|
|
scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
|
|
sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
|
|
|
|
} else {
|
|
/* Standard and fast speed */
|
|
fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
|
|
|
|
fsscll -= I2C_FASTSPEED_SCLL_TRIM;
|
|
fssclh -= I2C_FASTSPEED_SCLH_TRIM;
|
|
if (((fsscll < 0) || (fssclh < 0)) ||
|
|
((fsscll > 255) || (fssclh > 255))) {
|
|
printf("Error : I2C initializing clock\n");
|
|
return;
|
|
}
|
|
|
|
scll = (unsigned int)fsscll;
|
|
sclh = (unsigned int)fssclh;
|
|
}
|
|
|
|
writew(0x2, I2C_SYSC); /* for ES2 after soft reset */
|
|
udelay(1000);
|
|
writew(0x0, I2C_SYSC); /* will probably self clear but */
|
|
|
|
if (readw (I2C_CON) & I2C_CON_EN) {
|
|
writew (0, I2C_CON);
|
|
udelay (50000);
|
|
}
|
|
|
|
writew(psc, I2C_PSC);
|
|
writew(scll, I2C_SCLL);
|
|
writew(sclh, I2C_SCLH);
|
|
|
|
/* own address */
|
|
writew (slaveadd, I2C_OA);
|
|
writew (I2C_CON_EN, I2C_CON);
|
|
|
|
/* have to enable intrrupts or OMAP i2c module doesn't work */
|
|
writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
|
|
I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE);
|
|
udelay (1000);
|
|
flush_fifo();
|
|
writew (0xFFFF, I2C_STAT);
|
|
writew (0, I2C_CNT);
|
|
}
|
|
|
|
static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
|
|
{
|
|
int i2c_error = 0;
|
|
u16 status;
|
|
|
|
/* wait until bus not busy */
|
|
wait_for_bb ();
|
|
|
|
/* one byte only */
|
|
writew (1, I2C_CNT);
|
|
/* set slave address */
|
|
writew (devaddr, I2C_SA);
|
|
/* no stop bit needed here */
|
|
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
|
|
|
|
status = wait_for_pin ();
|
|
|
|
if (status & I2C_STAT_XRDY) {
|
|
/* Important: have to use byte access */
|
|
writeb (regoffset, I2C_DATA);
|
|
udelay (20000);
|
|
if (readw (I2C_STAT) & I2C_STAT_NACK) {
|
|
i2c_error = 1;
|
|
}
|
|
} else {
|
|
i2c_error = 1;
|
|
}
|
|
|
|
if (!i2c_error) {
|
|
/* free bus, otherwise we can't use a combined transction */
|
|
writew (0, I2C_CON);
|
|
while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) {
|
|
udelay (10000);
|
|
/* Have to clear pending interrupt to clear I2C_STAT */
|
|
writew (0xFFFF, I2C_STAT);
|
|
}
|
|
|
|
wait_for_bb ();
|
|
/* set slave address */
|
|
writew (devaddr, I2C_SA);
|
|
/* read one byte from slave */
|
|
writew (1, I2C_CNT);
|
|
/* need stop bit here */
|
|
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
|
|
I2C_CON);
|
|
|
|
status = wait_for_pin ();
|
|
if (status & I2C_STAT_RRDY) {
|
|
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
|
*value = readb (I2C_DATA);
|
|
#else
|
|
*value = readw (I2C_DATA);
|
|
#endif
|
|
udelay (20000);
|
|
} else {
|
|
i2c_error = 1;
|
|
}
|
|
|
|
if (!i2c_error) {
|
|
writew (I2C_CON_EN, I2C_CON);
|
|
while (readw (I2C_STAT)
|
|
|| (readw (I2C_CON) & I2C_CON_MST)) {
|
|
udelay (10000);
|
|
writew (0xFFFF, I2C_STAT);
|
|
}
|
|
}
|
|
}
|
|
flush_fifo();
|
|
writew (0xFFFF, I2C_STAT);
|
|
writew (0, I2C_CNT);
|
|
return i2c_error;
|
|
}
|
|
|
|
static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
|
|
{
|
|
int i2c_error = 0;
|
|
u16 status, stat;
|
|
|
|
/* wait until bus not busy */
|
|
wait_for_bb ();
|
|
|
|
/* two bytes */
|
|
writew (2, I2C_CNT);
|
|
/* set slave address */
|
|
writew (devaddr, I2C_SA);
|
|
/* stop bit needed here */
|
|
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
|
|
I2C_CON_STP, I2C_CON);
|
|
|
|
/* wait until state change */
|
|
status = wait_for_pin ();
|
|
|
|
if (status & I2C_STAT_XRDY) {
|
|
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
|
/* send out 1 byte */
|
|
writeb (regoffset, I2C_DATA);
|
|
writew (I2C_STAT_XRDY, I2C_STAT);
|
|
|
|
status = wait_for_pin ();
|
|
if ((status & I2C_STAT_XRDY)) {
|
|
/* send out next 1 byte */
|
|
writeb (value, I2C_DATA);
|
|
writew (I2C_STAT_XRDY, I2C_STAT);
|
|
} else {
|
|
i2c_error = 1;
|
|
}
|
|
#else
|
|
/* send out two bytes */
|
|
writew ((value << 8) + regoffset, I2C_DATA);
|
|
#endif
|
|
/* must have enough delay to allow BB bit to go low */
|
|
udelay (50000);
|
|
if (readw (I2C_STAT) & I2C_STAT_NACK) {
|
|
i2c_error = 1;
|
|
}
|
|
} else {
|
|
i2c_error = 1;
|
|
}
|
|
|
|
if (!i2c_error) {
|
|
int eout = 200;
|
|
|
|
writew (I2C_CON_EN, I2C_CON);
|
|
while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) {
|
|
udelay (1000);
|
|
/* have to read to clear intrrupt */
|
|
writew (0xFFFF, I2C_STAT);
|
|
if(--eout == 0) /* better leave with error than hang */
|
|
break;
|
|
}
|
|
}
|
|
flush_fifo();
|
|
writew (0xFFFF, I2C_STAT);
|
|
writew (0, I2C_CNT);
|
|
return i2c_error;
|
|
}
|
|
|
|
static void flush_fifo(void)
|
|
{ u16 stat;
|
|
|
|
/* note: if you try and read data when its not there or ready
|
|
* you get a bus error
|
|
*/
|
|
while(1){
|
|
stat = readw(I2C_STAT);
|
|
if(stat == I2C_STAT_RRDY){
|
|
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
|
readb(I2C_DATA);
|
|
#else
|
|
readw(I2C_DATA);
|
|
#endif
|
|
writew(I2C_STAT_RRDY,I2C_STAT);
|
|
udelay(1000);
|
|
}else
|
|
break;
|
|
}
|
|
}
|
|
|
|
int i2c_probe (uchar chip)
|
|
{
|
|
int res = 1; /* default = fail */
|
|
|
|
if (chip == readw (I2C_OA)) {
|
|
return res;
|
|
}
|
|
|
|
/* wait until bus not busy */
|
|
wait_for_bb ();
|
|
|
|
/* try to read one byte */
|
|
writew (1, I2C_CNT);
|
|
/* set slave address */
|
|
writew (chip, I2C_SA);
|
|
/* stop bit needed here */
|
|
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON);
|
|
/* enough delay for the NACK bit set */
|
|
udelay (50000);
|
|
|
|
if (!(readw (I2C_STAT) & I2C_STAT_NACK)) {
|
|
res = 0; /* success case */
|
|
flush_fifo();
|
|
writew(0xFFFF, I2C_STAT);
|
|
} else {
|
|
writew(0xFFFF, I2C_STAT); /* failue, clear sources*/
|
|
writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */
|
|
udelay(20000);
|
|
wait_for_bb ();
|
|
}
|
|
flush_fifo();
|
|
writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/
|
|
writew(0xFFFF, I2C_STAT);
|
|
return res;
|
|
}
|
|
|
|
int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
|
|
{
|
|
int i;
|
|
|
|
if (alen > 1) {
|
|
printf ("I2C read: addr len %d not supported\n", alen);
|
|
return 1;
|
|
}
|
|
|
|
if (addr + len > 256) {
|
|
printf ("I2C read: address out of range\n");
|
|
return 1;
|
|
}
|
|
|
|
for (i = 0; i < len; i++) {
|
|
if (i2c_read_byte (chip, addr + i, &buffer[i])) {
|
|
printf ("I2C read: I/O error\n");
|
|
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
|
|
{
|
|
int i;
|
|
|
|
if (alen > 1) {
|
|
printf ("I2C read: addr len %d not supported\n", alen);
|
|
return 1;
|
|
}
|
|
|
|
if (addr + len > 256) {
|
|
printf ("I2C read: address out of range\n");
|
|
return 1;
|
|
}
|
|
|
|
for (i = 0; i < len; i++) {
|
|
if (i2c_write_byte (chip, addr + i, buffer[i])) {
|
|
printf ("I2C read: I/O error\n");
|
|
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void wait_for_bb (void)
|
|
{
|
|
int timeout = 10;
|
|
u16 stat;
|
|
|
|
writew(0xFFFF, I2C_STAT); /* clear current interruts...*/
|
|
while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) {
|
|
writew (stat, I2C_STAT);
|
|
udelay (50000);
|
|
}
|
|
|
|
if (timeout <= 0) {
|
|
printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
|
|
readw (I2C_STAT));
|
|
}
|
|
writew(0xFFFF, I2C_STAT); /* clear delayed stuff*/
|
|
}
|
|
|
|
static u16 wait_for_pin (void)
|
|
{
|
|
u16 status;
|
|
int timeout = 10;
|
|
|
|
do {
|
|
udelay (1000);
|
|
status = readw (I2C_STAT);
|
|
} while ( !(status &
|
|
(I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
|
|
I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
|
|
I2C_STAT_AL)) && timeout--);
|
|
|
|
if (timeout <= 0) {
|
|
printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
|
|
readw (I2C_STAT));
|
|
writew(0xFFFF, I2C_STAT);
|
|
}
|
|
return status;
|
|
}
|