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https://github.com/brain-hackers/u-boot-brain
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0c1456d571
When a crash occurs in thumb mode the crash dump is incorrect. This is due to the usage of a non-existing configuration variable CONFIG_ARM_THUMB in the definition of macro thumb_mode(regs). Use CONFIG_IS_ENABLED(SYS_THUMB_BUILD) to detect that the code has been compiled for thumb mode. Remove ARM_THUMB from config_whitelist.txt. With the patch crash dumps indicate thumb mode correctly. On a system with thumb mode: => exception unaligned data abort pc : [<8f7a2b52>] lr : [<8f7ab1ef>] reloc pc : [<1780cb52>] lr : [<178151ef>] sp : 8ed8c3f8 ip : 8f7a2b4d fp : 00000002 r10: 8f7f8228 r9 : 8ed95ea8 r8 : 8ed99488 r7 : 8f7ab141 r6 : 00000000 r5 : 8ed8c3f9 r4 : 8f7f6390 r3 : 8ed9948c r2 : 00000001 r1 : 00000000 r0 : 8f7f6390 Flags: nzCv IRQs off FIQs off Mode SVC_32 (T) Code: 8f7e 466d f105 0501 (e9d5) 6700 The Flags line has '(T)' and in the Code line the output is in u16 groups. On a system without thumb mode: => exception breakpoint prefetch abort pc : [<7ff5a5c8>] lr : [<7ff675ec>] reloc pc : [<0000e5c8>] lr : [<0001b5ec>] sp : 7ee0ad80 ip : 7ff5a5cc fp : 7ff674cc r10: 00000002 r9 : 7ef0bed8 r8 : 7ffd6214 r7 : 7ef0e080 r6 : 00000000 r5 : 7ffd4090 r4 : 00000000 r3 : 7ef0e084 r2 : 00000001 r1 : 00000000 r0 : 7ffd4090 Flags: nzCv IRQs off FIQs off Mode SVC_32 Code: e1a0500d e2855001 e1c560d0 e3a00001 (e12fff1e) The Flags line does not show '(T)' and in the Code line the output is in u32 groups. Reported-by: Marek Vasut <marex@denx.de> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Marek Vasut <marex@denx.de>
132 lines
2.7 KiB
C
132 lines
2.7 KiB
C
/*
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* linux/include/asm-arm/proc-armv/ptrace.h
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*
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* Copyright (C) 1996-1999 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PROC_PTRACE_H
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#define __ASM_PROC_PTRACE_H
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#ifdef CONFIG_ARM64
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#define PCMASK 0
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#ifndef __ASSEMBLY__
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/*
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* This struct defines the way the registers are stored
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* on the stack during an exception.
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*/
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struct pt_regs {
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unsigned long elr;
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unsigned long regs[31];
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};
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#endif /* __ASSEMBLY__ */
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#else /* CONFIG_ARM64 */
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#define USR26_MODE 0x00
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#define FIQ26_MODE 0x01
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#define IRQ26_MODE 0x02
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#define SVC26_MODE 0x03
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#define USR_MODE 0x10
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#define FIQ_MODE 0x11
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#define IRQ_MODE 0x12
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#define SVC_MODE 0x13
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#define MON_MODE 0x16
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#define ABT_MODE 0x17
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#define HYP_MODE 0x1a
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#define UND_MODE 0x1b
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#define SYSTEM_MODE 0x1f
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#define MODE_MASK 0x1f
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#define T_BIT 0x20
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#define F_BIT 0x40
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#define I_BIT 0x80
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#define A_BIT 0x100
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#define CC_V_BIT (1 << 28)
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#define CC_C_BIT (1 << 29)
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#define CC_Z_BIT (1 << 30)
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#define CC_N_BIT (1 << 31)
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#define PCMASK 0
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#ifndef __ASSEMBLY__
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/* this struct defines the way the registers are stored on the
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stack during a system call. */
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struct pt_regs {
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long uregs[18];
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};
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#define ARM_cpsr uregs[16]
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#define ARM_pc uregs[15]
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#define ARM_lr uregs[14]
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#define ARM_sp uregs[13]
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#define ARM_ip uregs[12]
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#define ARM_fp uregs[11]
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#define ARM_r10 uregs[10]
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#define ARM_r9 uregs[9]
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#define ARM_r8 uregs[8]
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#define ARM_r7 uregs[7]
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#define ARM_r6 uregs[6]
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#define ARM_r5 uregs[5]
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#define ARM_r4 uregs[4]
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#define ARM_r3 uregs[3]
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#define ARM_r2 uregs[2]
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#define ARM_r1 uregs[1]
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#define ARM_r0 uregs[0]
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#define ARM_ORIG_r0 uregs[17]
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#ifdef __KERNEL__
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#define user_mode(regs) \
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(((regs)->ARM_cpsr & 0xf) == 0)
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#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
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#define thumb_mode(regs) \
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(((regs)->ARM_cpsr & T_BIT))
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#else
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#define thumb_mode(regs) (0)
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#endif
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#define processor_mode(regs) \
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((regs)->ARM_cpsr & MODE_MASK)
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#define interrupts_enabled(regs) \
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(!((regs)->ARM_cpsr & I_BIT))
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#define fast_interrupts_enabled(regs) \
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(!((regs)->ARM_cpsr & F_BIT))
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#define condition_codes(regs) \
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((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
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/* Are the current registers suitable for user mode?
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* (used to maintain security in signal handlers)
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*/
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static inline int valid_user_regs(struct pt_regs *regs)
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{
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if ((regs->ARM_cpsr & 0xf) == 0 &&
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(regs->ARM_cpsr & (F_BIT|I_BIT)) == 0)
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return 1;
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/*
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* Force CPSR to something logical...
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*/
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regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10);
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return 0;
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}
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_ARM64 */
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#endif
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