mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
97 lines
3.0 KiB
C
97 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _ARCH_EMC_H_
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#define _ARCH_EMC_H_
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#include <asm/types.h>
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#define TEGRA_EMC_NUM_REGS 46
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/* EMC Registers */
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struct emc_ctlr {
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u32 cfg; /* 0x00: EMC_CFG */
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u32 reserved0[3]; /* 0x04 ~ 0x0C */
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u32 adr_cfg; /* 0x10: EMC_ADR_CFG */
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u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */
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u32 reserved1[2]; /* 0x18 ~ 0x18 */
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u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */
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u32 pin; /* 0x24: EMC_PIN */
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u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */
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u32 rc; /* 0x2C: EMC_RC */
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u32 rfc; /* 0x30: EMC_RFC */
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u32 ras; /* 0x34: EMC_RAS */
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u32 rp; /* 0x38: EMC_RP */
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u32 r2w; /* 0x3C: EMC_R2W */
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u32 w2r; /* 0x40: EMC_W2R */
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u32 r2p; /* 0x44: EMC_R2P */
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u32 w2p; /* 0x48: EMC_W2P */
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u32 rd_rcd; /* 0x4C: EMC_RD_RCD */
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u32 wd_rcd; /* 0x50: EMC_WD_RCD */
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u32 rrd; /* 0x54: EMC_RRD */
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u32 rext; /* 0x58: EMC_REXT */
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u32 wdv; /* 0x5C: EMC_WDV */
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u32 quse; /* 0x60: EMC_QUSE */
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u32 qrst; /* 0x64: EMC_QRST */
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u32 qsafe; /* 0x68: EMC_QSAFE */
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u32 rdv; /* 0x6C: EMC_RDV */
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u32 refresh; /* 0x70: EMC_REFRESH */
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u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */
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u32 pdex2wr; /* 0x78: EMC_PDEX2WR */
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u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */
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u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */
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u32 act2pden; /* 0x84: EMC_ACT2PDEN */
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u32 ar2pden; /* 0x88: EMC_AR2PDEN */
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u32 rw2pden; /* 0x8C: EMC_RW2PDEN */
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u32 txsr; /* 0x90: EMC_TXSR */
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u32 tcke; /* 0x94: EMC_TCKE */
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u32 tfaw; /* 0x98: EMC_TFAW */
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u32 trpab; /* 0x9C: EMC_TRPAB */
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u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */
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u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */
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u32 trefbw; /* 0xA8: EMC_TREFBW */
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u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */
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u32 odt_write; /* 0xB0: EMC_ODT_WRITE */
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u32 odt_read; /* 0xB4: EMC_ODT_READ */
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u32 reserved2[5]; /* 0xB8 ~ 0xC8 */
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u32 mrs; /* 0xCC: EMC_MRS */
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u32 emrs; /* 0xD0: EMC_EMRS */
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u32 ref; /* 0xD4: EMC_REF */
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u32 pre; /* 0xD8: EMC_PRE */
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u32 nop; /* 0xDC: EMC_NOP */
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u32 self_ref; /* 0xE0: EMC_SELF_REF */
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u32 dpd; /* 0xE4: EMC_DPD */
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u32 mrw; /* 0xE8: EMC_MRW */
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u32 mrr; /* 0xEC: EMC_MRR */
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u32 reserved3; /* 0xF0: */
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u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */
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u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */
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u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */
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u32 fbio_spare; /* 0x100: SBIO_SPARE */
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/* There are more registers ... */
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};
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/**
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* Set up the EMC for the given rate. The timing parameters are retrieved
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* from the device tree "nvidia,tegra20-emc" node and its
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* "nvidia,tegra20-emc-table" sub-nodes.
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*
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* @param blob Device tree blob
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* @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
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* @return 0 if ok, else -ve error code (look in emc.c to decode it)
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*/
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int tegra_set_emc(const void *blob, unsigned rate);
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/**
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* Get a pointer to the EMC controller from the device tree.
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*
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* @param blob Device tree blob
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* @return pointer to EMC controller
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*/
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struct emc_ctlr *emc_get_controller(const void *blob);
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#endif
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