mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
73 lines
3.9 KiB
C
73 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#ifndef _ASM_ARCH_HARDWARE_H
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#define _ASM_ARCH_HARDWARE_H
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/* STV0991 */
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#define SRAM0_BASE_ADDR 0x00000000UL
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#define SRAM1_BASE_ADDR 0x00068000UL
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#define SRAM2_BASE_ADDR 0x000D0000UL
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#define SRAM3_BASE_ADDR 0x00138000UL
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#define CFS_SRAM0_BASE_ADDR 0x00198000UL
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#define CFS_SRAM1_BASE_ADDR 0x001B8000UL
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#define FAST_SRAM_BASE_ADDR 0x001D8000UL
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#define FLASH_BASE_ADDR 0x40000000UL
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#define PL310_BASE_ADDR 0x70000000UL
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#define HSAXIM_BASE_ADDR 0x70100000UL
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#define IMGSS_BASE_ADDR 0x70200000UL
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#define ADC_BASE_ADDR 0x80000000UL
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#define GPIOA_BASE_ADDR 0x80001000UL
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#define GPIOB_BASE_ADDR 0x80002000UL
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#define GPIOC_BASE_ADDR 0x80003000UL
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#define HDM_BASE_ADDR 0x80004000UL
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#define THSENS_BASE_ADDR 0x80200000UL
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#define GPTIMER2_BASE_ADDR 0x80201000UL
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#define GPTIMER1_BASE_ADDR 0x80202000UL
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#define QSPI_BASE_ADDR 0x80203000UL
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#define CGU_BASE_ADDR 0x80204000UL
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#define CREG_BASE_ADDR 0x80205000UL
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#define PEC_BASE_ADDR 0x80206000UL
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#define WDRU_BASE_ADDR 0x80207000UL
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#define BSEC_BASE_ADDR 0x80208000UL
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#define DAP_ROM_BASE_ADDR 0x80210000UL
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#define SOC_CTI_BASE_ADDR 0x80211000UL
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#define TPIU_BASE_ADDR 0x80212000UL
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#define TMC_ETF_BASE_ADDR 0x80213000UL
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#define R4_ETM_BASE_ADDR 0x80214000UL
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#define R4_CTI_BASE_ADDR 0x80215000UL
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#define R4_DBG_BASE_ADDR 0x80216000UL
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#define GMAC_BASE_ADDR 0x80300000UL
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#define RNSS_BASE_ADDR 0x80302000UL
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#define CRYP_BASE_ADDR 0x80303000UL
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#define HASH_BASE_ADDR 0x80304000UL
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#define GPDMA_BASE_ADDR 0x80305000UL
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#define ISA_BASE_ADDR 0x8032A000UL
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#define HCI_BASE_ADDR 0x80400000UL
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#define I2C1_BASE_ADDR 0x80401000UL
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#define I2C2_BASE_ADDR 0x80402000UL
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#define SAI_BASE_ADDR 0x80403000UL
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#define USI_BASE_ADDR 0x80404000UL
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#define SPI1_BASE_ADDR 0x80405000UL
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#define UART_BASE_ADDR 0x80406000UL
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#define SPI2_BASE_ADDR 0x80500000UL
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#define CAN_BASE_ADDR 0x80501000UL
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#define USART1_BASE_ADDR 0x80502000UL
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#define USART2_BASE_ADDR 0x80503000UL
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#define USART3_BASE_ADDR 0x80504000UL
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#define USART4_BASE_ADDR 0x80505000UL
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#define USART5_BASE_ADDR 0x80506000UL
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#define USART6_BASE_ADDR 0x80507000UL
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#define SDI2_BASE_ADDR 0x80600000UL
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#define SDI1_BASE_ADDR 0x80601000UL
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#define VICA_BASE_ADDR 0x81000000UL
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#define VICB_BASE_ADDR 0x81001000UL
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#define STM_CHANNELS_BASE_ADDR 0x81100000UL
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#define STM_BASE_ADDR 0x81110000UL
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#define SROM_BASE_ADDR 0xFFFF0000UL
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#endif /* _ASM_ARCH_HARDWARE_H */
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