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https://github.com/brain-hackers/u-boot-brain
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e230c579a3
reset cause is a generic functionality based on the soc cru registers in rockchip. This can be used for printing the cause of reset in cpuinfo or some other place where reset cause is needed. Other than cpuinfo, reset cause can also be using during bootcount for checking the specific reset cause and glow the led based on the reset cause. So, let's separate the reset cause code from cpuinfo, and add a check to build it for rk3399, rk3288 since these two soc are supporting reset cause as of now. Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
36 lines
732 B
C
36 lines
732 B
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* (C) Copyright 2019 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#ifndef _ROCKCHIP_CLOCK_H
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#define _ROCKCHIP_CLOCK_H
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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#if defined(CONFIG_ROCKCHIP_RK3288)
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# include <asm/arch-rockchip/cru_rk3288.h>
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#elif defined(CONFIG_ROCKCHIP_RK3399)
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# include <asm/arch-rockchip/cru_rk3399.h>
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#endif
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/* CRU_GLB_RST_ST */
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enum {
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GLB_POR_RST,
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FST_GLB_RST_ST = BIT(0),
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SND_GLB_RST_ST = BIT(1),
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FST_GLB_TSADC_RST_ST = BIT(2),
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SND_GLB_TSADC_RST_ST = BIT(3),
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FST_GLB_WDT_RST_ST = BIT(4),
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SND_GLB_WDT_RST_ST = BIT(5),
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};
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#define MHz 1000000
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char *get_reset_cause(void);
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#endif /* _ROCKCHIP_CLOCK_H */
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