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https://github.com/brain-hackers/u-boot-brain
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387d321add
Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>
429 lines
12 KiB
C
429 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#ifndef __CSRS_XCV_H__
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#define __CSRS_XCV_H__
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/**
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* @file
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*
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* Configuration and status register (CSR) address and type definitions for
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* XCV.
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*
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* This file is auto generated. Do not edit.
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*
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*/
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/**
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* Enumeration xcv_bar_e
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*
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* XCV Base Address Register Enumeration Enumerates the base address
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* registers.
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*/
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#define XCV_BAR_E_XCVX_PF_BAR0(a) (0x87e0db000000ll + 0ll * (a))
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#define XCV_BAR_E_XCVX_PF_BAR0_SIZE 0x100000ull
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#define XCV_BAR_E_XCVX_PF_BAR4(a) (0x87e0dbf00000ll + 0ll * (a))
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#define XCV_BAR_E_XCVX_PF_BAR4_SIZE 0x100000ull
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/**
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* Enumeration xcv_int_vec_e
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*
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* XCV MSI-X Vector Enumeration Enumerates the MSI-X interrupt vectors.
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*/
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#define XCV_INT_VEC_E_INT (0)
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/**
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* Register (RSL) xcv#_batch_crd_ret
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*
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* XCV Batch Credit Return Register
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*/
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union xcvx_batch_crd_ret {
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u64 u;
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struct xcvx_batch_crd_ret_s {
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u64 crd_ret : 1;
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u64 reserved_1_63 : 63;
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} s;
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/* struct xcvx_batch_crd_ret_s cn; */
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};
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static inline u64 XCVX_BATCH_CRD_RET(u64 a)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_BATCH_CRD_RET(u64 a)
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{
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return 0x100 + 0 * a;
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}
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/**
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* Register (RSL) xcv#_comp_ctl
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*
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* XCV Compensation Controller Register This register controls
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* programmable compensation.
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*/
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union xcvx_comp_ctl {
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u64 u;
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struct xcvx_comp_ctl_s {
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u64 nctl_sat : 1;
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u64 reserved_1_26 : 26;
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u64 nctl_lock : 1;
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u64 reserved_28 : 1;
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u64 pctl_sat : 1;
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u64 pctl_lock : 1;
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u64 reserved_31 : 1;
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u64 drv_nctl : 5;
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u64 reserved_37_39 : 3;
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u64 drv_pctl : 5;
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u64 reserved_45_47 : 3;
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u64 cmp_nctl : 5;
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u64 reserved_53_55 : 3;
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u64 cmp_pctl : 5;
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u64 reserved_61_62 : 2;
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u64 drv_byp : 1;
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} s;
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/* struct xcvx_comp_ctl_s cn; */
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};
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static inline u64 XCVX_COMP_CTL(u64 a)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_COMP_CTL(u64 a)
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{
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return 0x20 + 0 * a;
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}
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/**
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* Register (RSL) xcv#_ctl
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*
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* XCV Control Register This register contains the status control bits.
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*/
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union xcvx_ctl {
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u64 u;
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struct xcvx_ctl_s {
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u64 speed : 2;
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u64 lpbk_int : 1;
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u64 lpbk_ext : 1;
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u64 reserved_4_63 : 60;
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} s;
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/* struct xcvx_ctl_s cn; */
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};
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static inline u64 XCVX_CTL(u64 a)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_CTL(u64 a)
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{
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return 0x30 + 0 * a;
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}
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/**
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* Register (RSL) xcv#_dll_ctl
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*
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* XCV DLL Controller Register The RGMII timing specification requires
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* that devices transmit clock and data synchronously. The specification
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* requires external sources (namely the PC board trace routes) to
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* introduce the appropriate 1.5 to 2.0 ns of delay. To eliminate the
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* need for the PC board delays, the RGMII interface has optional on-
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* board DLLs for both transmit and receive. For correct operation, at
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* most one of the transmitter, board, or receiver involved in an RGMII
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* link should introduce delay. By default/reset, the RGMII receivers
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* delay the received clock, and the RGMII transmitters do not delay the
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* transmitted clock. Whether this default works as-is with a given link
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* partner depends on the behavior of the link partner and the PC board.
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* These are the possible modes of RGMII receive operation: *
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* XCV()_DLL_CTL[CLKRX_BYP] = 0 (reset value) - The RGMII receive
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* interface introduces clock delay using its internal DLL. This mode is
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* appropriate if neither the remote transmitter nor the PC board delays
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* the clock. * XCV()_DLL_CTL[CLKRX_BYP] = 1, [CLKRX_SET] = 0x0 - The
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* RGMII receive interface introduces no clock delay. This mode is
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* appropriate if either the remote transmitter or the PC board delays
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* the clock. These are the possible modes of RGMII transmit operation:
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* * XCV()_DLL_CTL[CLKTX_BYP] = 1, [CLKTX_SET] = 0x0 (reset value) - The
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* RGMII transmit interface introduces no clock delay. This mode is
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* appropriate is either the remote receiver or the PC board delays the
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* clock. * XCV()_DLL_CTL[CLKTX_BYP] = 0 - The RGMII transmit interface
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* introduces clock delay using its internal DLL. This mode is
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* appropriate if neither the remote receiver nor the PC board delays the
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* clock.
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*/
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union xcvx_dll_ctl {
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u64 u;
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struct xcvx_dll_ctl_s {
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u64 refclk_sel : 2;
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u64 reserved_2_7 : 6;
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u64 clktx_set : 7;
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u64 clktx_byp : 1;
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u64 clkrx_set : 7;
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u64 clkrx_byp : 1;
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u64 clk_set : 7;
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u64 lock : 1;
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u64 reserved_32_63 : 32;
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} s;
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/* struct xcvx_dll_ctl_s cn; */
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};
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static inline u64 XCVX_DLL_CTL(u64 a)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_DLL_CTL(u64 a)
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{
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return 0x10 + 0 * a;
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}
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/**
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* Register (RSL) xcv#_eco
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*
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* INTERNAL: XCV ECO Register
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*/
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union xcvx_eco {
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u64 u;
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struct xcvx_eco_s {
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u64 eco_rw : 16;
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u64 reserved_16_63 : 48;
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} s;
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/* struct xcvx_eco_s cn; */
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};
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static inline u64 XCVX_ECO(u64 a)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_ECO(u64 a)
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{
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return 0x200 + 0 * a;
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}
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/**
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* Register (RSL) xcv#_inbnd_status
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*
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* XCV Inband Status Register This register contains RGMII inband status.
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*/
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union xcvx_inbnd_status {
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u64 u;
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struct xcvx_inbnd_status_s {
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u64 link : 1;
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u64 speed : 2;
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u64 duplex : 1;
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u64 reserved_4_63 : 60;
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} s;
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/* struct xcvx_inbnd_status_s cn; */
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};
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static inline u64 XCVX_INBND_STATUS(u64 a)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_INBND_STATUS(u64 a)
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{
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return 0x80 + 0 * a;
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}
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/**
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* Register (RSL) xcv#_int
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*
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* XCV Interrupt Register This register flags error for TX FIFO overflow,
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* TX FIFO underflow and incomplete byte for 10/100 Mode. It also flags
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* status change for link duplex, link speed and link up/down.
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*/
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union xcvx_int {
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u64 u;
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struct xcvx_int_s {
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u64 link : 1;
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u64 speed : 1;
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u64 reserved_2 : 1;
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u64 duplex : 1;
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u64 incomp_byte : 1;
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u64 tx_undflw : 1;
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u64 tx_ovrflw : 1;
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u64 reserved_7_63 : 57;
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} s;
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/* struct xcvx_int_s cn; */
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};
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static inline u64 XCVX_INT(u64 a)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_INT(u64 a)
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{
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return 0x40 + 0 * a;
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}
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/**
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* Register (RSL) xcv#_int_ena_w1c
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*
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* Loopback Error Interrupt Enable Clear Register This register clears
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* interrupt enable bits.
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*/
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union xcvx_int_ena_w1c {
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u64 u;
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struct xcvx_int_ena_w1c_s {
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u64 link : 1;
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u64 speed : 1;
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u64 reserved_2 : 1;
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u64 duplex : 1;
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u64 incomp_byte : 1;
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u64 tx_undflw : 1;
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u64 tx_ovrflw : 1;
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u64 reserved_7_63 : 57;
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} s;
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/* struct xcvx_int_ena_w1c_s cn; */
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};
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static inline u64 XCVX_INT_ENA_W1C(u64 a)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_INT_ENA_W1C(u64 a)
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{
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return 0x50 + 0 * a;
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}
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/**
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* Register (RSL) xcv#_int_ena_w1s
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*
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* Loopback Error Interrupt Enable Set Register This register sets
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* interrupt enable bits.
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*/
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union xcvx_int_ena_w1s {
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u64 u;
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struct xcvx_int_ena_w1s_s {
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u64 link : 1;
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u64 speed : 1;
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u64 reserved_2 : 1;
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u64 duplex : 1;
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u64 incomp_byte : 1;
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u64 tx_undflw : 1;
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u64 tx_ovrflw : 1;
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u64 reserved_7_63 : 57;
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} s;
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/* struct xcvx_int_ena_w1s_s cn; */
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};
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static inline u64 XCVX_INT_ENA_W1S(u64 a)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_INT_ENA_W1S(u64 a)
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{
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return 0x58 + 0 * a;
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}
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/**
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* Register (RSL) xcv#_int_w1s
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*
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* Loopback Error Interrupt Set Register This register sets interrupt
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* bits.
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*/
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union xcvx_int_w1s {
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u64 u;
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struct xcvx_int_w1s_s {
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u64 link : 1;
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u64 speed : 1;
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u64 reserved_2 : 1;
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u64 duplex : 1;
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u64 incomp_byte : 1;
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u64 tx_undflw : 1;
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u64 tx_ovrflw : 1;
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u64 reserved_7_63 : 57;
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} s;
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/* struct xcvx_int_w1s_s cn; */
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};
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static inline u64 XCVX_INT_W1S(u64 a)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_INT_W1S(u64 a)
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{
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return 0x48 + 0 * a;
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}
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/**
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* Register (RSL) xcv#_msix_pba#
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*
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* XCV MSI-X Pending Bit Array Registers This register is the MSI-X PBA
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* table; the bit number is indexed by the XCV_INT_VEC_E enumeration.
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*/
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union xcvx_msix_pbax {
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u64 u;
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struct xcvx_msix_pbax_s {
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u64 pend : 64;
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} s;
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/* struct xcvx_msix_pbax_s cn; */
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};
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static inline u64 XCVX_MSIX_PBAX(u64 a, u64 b)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_MSIX_PBAX(u64 a, u64 b)
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{
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return 0xf0000 + 0 * a + 8 * b;
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}
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/**
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* Register (RSL) xcv#_msix_vec#_addr
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*
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* XCV MSI-X Vector-Table Address Register This register is the MSI-X
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* vector table, indexed by the XCV_INT_VEC_E enumeration.
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*/
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union xcvx_msix_vecx_addr {
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u64 u;
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struct xcvx_msix_vecx_addr_s {
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u64 secvec : 1;
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u64 reserved_1 : 1;
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u64 addr : 47;
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u64 reserved_49_63 : 15;
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} s;
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/* struct xcvx_msix_vecx_addr_s cn; */
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};
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static inline u64 XCVX_MSIX_VECX_ADDR(u64 a, u64 b)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_MSIX_VECX_ADDR(u64 a, u64 b)
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{
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return 0 + 0 * a + 0x10 * b;
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}
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/**
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* Register (RSL) xcv#_msix_vec#_ctl
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*
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* XCV MSI-X Vector-Table Control and Data Register This register is the
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* MSI-X vector table, indexed by the XCV_INT_VEC_E enumeration.
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*/
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union xcvx_msix_vecx_ctl {
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u64 u;
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struct xcvx_msix_vecx_ctl_s {
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u64 data : 20;
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u64 reserved_20_31 : 12;
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u64 mask : 1;
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u64 reserved_33_63 : 31;
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} s;
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/* struct xcvx_msix_vecx_ctl_s cn; */
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};
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static inline u64 XCVX_MSIX_VECX_CTL(u64 a, u64 b)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_MSIX_VECX_CTL(u64 a, u64 b)
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{
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return 8 + 0 * a + 0x10 * b;
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}
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/**
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* Register (RSL) xcv#_reset
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*
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* XCV Reset Registers This register controls reset.
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*/
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union xcvx_reset {
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u64 u;
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struct xcvx_reset_s {
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u64 rx_dat_rst_n : 1;
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u64 rx_pkt_rst_n : 1;
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u64 tx_dat_rst_n : 1;
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u64 tx_pkt_rst_n : 1;
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u64 reserved_4_6 : 3;
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u64 comp : 1;
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u64 reserved_8_10 : 3;
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u64 dllrst : 1;
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u64 reserved_12_14 : 3;
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u64 clkrst : 1;
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u64 reserved_16_62 : 47;
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u64 enable : 1;
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} s;
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/* struct xcvx_reset_s cn; */
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};
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static inline u64 XCVX_RESET(u64 a)
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__attribute__ ((pure, always_inline));
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static inline u64 XCVX_RESET(u64 a)
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{
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return 0 + 0 * a;
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}
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#endif /* __CSRS_XCV_H__ */
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