mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
66d9427403
The registers which are managed by the meson-gxl-usb3 PHY driver are actually "USB control" registers (which are "glue" registers which manage OTG detection and routing of the OTG capable port between the DWC2 peripheral-only controller and the DWC3 host-only controller). Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-gxl-usb driver supports the USB control registers on GXL and GXM SoCs (these were previously managed by the meson-gxl-usb3 PHY driver). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
18 lines
445 B
C
18 lines
445 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright 2019 BayLibre SAS
|
|
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
|
*/
|
|
#ifndef _ARCH_MESON_USB_GX_H_
|
|
#define _ARCH_MESON_USB_GX_H_
|
|
|
|
#include <generic-phy.h>
|
|
#include <linux/usb/otg.h>
|
|
|
|
/* TOFIX add set_mode to struct phy_ops */
|
|
void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode);
|
|
|
|
int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode);
|
|
|
|
#endif
|