mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*/
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#ifndef _LPC32XX_TIMER_H
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#define _LPC32XX_TIMER_H
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#include <asm/types.h>
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/* Timer/Counter Registers */
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struct timer_regs {
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u32 ir; /* Interrupt Register */
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u32 tcr; /* Timer Control Register */
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u32 tc; /* Timer Counter */
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u32 pr; /* Prescale Register */
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u32 pc; /* Prescale Counter */
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u32 mcr; /* Match Control Register */
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u32 mr[4]; /* Match Registers */
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u32 ccr; /* Capture Control Register */
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u32 cr[4]; /* Capture Registers */
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u32 emr; /* External Match Register */
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u32 reserved[12];
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u32 ctcr; /* Count Control Register */
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};
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/* Timer/Counter Interrupt Register bits */
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#define TIMER_IR_CR(n) (1 << ((n) + 4))
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#define TIMER_IR_MR(n) (1 << (n))
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/* Timer/Counter Timer Control Register bits */
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#define TIMER_TCR_COUNTER_RESET (1 << 1)
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#define TIMER_TCR_COUNTER_ENABLE (1 << 0)
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#define TIMER_TCR_COUNTER_DISABLE (0 << 0)
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/* Timer/Counter Match Control Register bits */
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#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2))
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#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1))
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#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n)))
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/* Timer/Counter Capture Control Register bits */
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#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2))
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#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1))
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#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n)))
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/* Timer/Counter External Match Register bits */
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#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4))
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#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4))
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#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4))
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#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4))
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#define TIMER_EMR_EM(n) (1 << (n))
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/* Timer/Counter Count Control Register bits */
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#define TIMER_CTCR_INPUT(n) ((n) << 2)
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#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0)
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#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0)
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#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0)
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#define TIMER_CTCR_MODE_TIMER (0x0 << 0)
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#endif /* _LPC32XX_TIMER_H */
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