mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
162 lines
3.6 KiB
C
162 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
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*/
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#ifndef _ARMADA100CPU_H
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#define _ARMADA100CPU_H
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#include <asm/io.h>
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#include <asm/system.h>
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/*
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* Main Power Management (MPMU) Registers
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* Refer Datasheet Appendix A.8
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*/
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struct armd1mpmu_registers {
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u8 pad0[0x08 - 0x00];
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u32 fccr; /*0x0008*/
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u32 pocr; /*0x000c*/
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u32 posr; /*0x0010*/
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u32 succr; /*0x0014*/
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u8 pad1[0x030 - 0x014 - 4];
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u32 gpcr; /*0x0030*/
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u8 pad2[0x200 - 0x030 - 4];
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u32 wdtpcr; /*0x0200*/
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u8 pad3[0x1000 - 0x200 - 4];
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u32 apcr; /*0x1000*/
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u32 apsr; /*0x1004*/
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u8 pad4[0x1020 - 0x1004 - 4];
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u32 aprr; /*0x1020*/
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u32 acgr; /*0x1024*/
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u32 arsr; /*0x1028*/
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};
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/*
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* Application Subsystem Power Management
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* Refer Datasheet Appendix A.9
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*/
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struct armd1apmu_registers {
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u32 pcr; /* 0x000 */
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u32 ccr; /* 0x004 */
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u32 pad1;
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u32 ccsr; /* 0x00C */
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u32 fc_timer; /* 0x010 */
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u32 pad2;
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u32 ideal_cfg; /* 0x018 */
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u8 pad3[0x04C - 0x018 - 4];
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u32 lcdcrc; /* 0x04C */
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u32 cciccrc; /* 0x050 */
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u32 sd1crc; /* 0x054 */
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u32 sd2crc; /* 0x058 */
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u32 usbcrc; /* 0x05C */
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u32 nfccrc; /* 0x060 */
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u32 dmacrc; /* 0x064 */
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u32 pad4;
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u32 buscrc; /* 0x06C */
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u8 pad5[0x07C - 0x06C - 4];
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u32 wake_clr; /* 0x07C */
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u8 pad6[0x090 - 0x07C - 4];
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u32 core_status; /* 0x090 */
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u32 rfsc; /* 0x094 */
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u32 imr; /* 0x098 */
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u32 irwc; /* 0x09C */
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u32 isr; /* 0x0A0 */
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u8 pad7[0x0B0 - 0x0A0 - 4];
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u32 mhst; /* 0x0B0 */
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u32 msr; /* 0x0B4 */
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u8 pad8[0x0C0 - 0x0B4 - 4];
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u32 msst; /* 0x0C0 */
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u32 pllss; /* 0x0C4 */
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u32 smb; /* 0x0C8 */
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u32 gccrc; /* 0x0CC */
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u8 pad9[0x0D4 - 0x0CC - 4];
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u32 smccrc; /* 0x0D4 */
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u32 pad10;
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u32 xdcrc; /* 0x0DC */
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u32 sd3crc; /* 0x0E0 */
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u32 sd4crc; /* 0x0E4 */
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u8 pad11[0x0F0 - 0x0E4 - 4];
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u32 cfcrc; /* 0x0F0 */
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u32 mspcrc; /* 0x0F4 */
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u32 cmucrc; /* 0x0F8 */
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u32 fecrc; /* 0x0FC */
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u32 pciecrc; /* 0x100 */
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u32 epdcrc; /* 0x104 */
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};
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/*
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* APB1 Clock Reset/Control Registers
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* Refer Datasheet Appendix A.10
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*/
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struct armd1apb1_registers {
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u32 uart1; /*0x000*/
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u32 uart2; /*0x004*/
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u32 gpio; /*0x008*/
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u32 pwm1; /*0x00c*/
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u32 pwm2; /*0x010*/
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u32 pwm3; /*0x014*/
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u32 pwm4; /*0x018*/
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u8 pad0[0x028 - 0x018 - 4];
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u32 rtc; /*0x028*/
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u32 twsi0; /*0x02c*/
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u32 kpc; /*0x030*/
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u32 timers; /*0x034*/
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u8 pad1[0x03c - 0x034 - 4];
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u32 aib; /*0x03c*/
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u32 sw_jtag; /*0x040*/
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u32 timer1; /*0x044*/
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u32 onewire; /*0x048*/
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u8 pad2[0x050 - 0x048 - 4];
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u32 asfar; /*0x050 AIB Secure First Access Reg*/
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u32 assar; /*0x054 AIB Secure Second Access Reg*/
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u8 pad3[0x06c - 0x054 - 4];
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u32 twsi1; /*0x06c*/
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u32 uart3; /*0x070*/
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u8 pad4[0x07c - 0x070 - 4];
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u32 timer2; /*0x07C*/
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u8 pad5[0x084 - 0x07c - 4];
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u32 ac97; /*0x084*/
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};
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/*
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* APB2 Clock Reset/Control Registers
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* Refer Datasheet Appendix A.11
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*/
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struct armd1apb2_registers {
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u32 pad1[0x01C - 0x000];
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u32 ssp1_clkrst; /* 0x01C */
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u32 ssp2_clkrst; /* 0x020 */
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u32 pad2[0x04C - 0x020 - 4];
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u32 ssp3_clkrst; /* 0x04C */
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u32 pad3[0x058 - 0x04C - 4];
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u32 ssp4_clkrst; /* 0x058 */
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u32 ssp5_clkrst; /* 0x05C */
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};
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/*
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* CPU Interface Registers
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* Refer Datasheet Appendix A.2
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*/
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struct armd1cpu_registers {
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u32 chip_id; /* Chip Id Reg */
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u32 pad;
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u32 cpu_conf; /* CPU Conf Reg */
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u32 pad1;
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u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
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u32 pad2;
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u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
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u32 mcb_conf; /* MCB Conf Reg */
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u32 sys_boot_ctl; /* Sytem Boot Control */
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};
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/*
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* Functions
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*/
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u32 armd1_sdram_base(int);
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u32 armd1_sdram_size(int);
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#endif /* _ARMADA100CPU_H */
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