mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
90 lines
2.2 KiB
C
90 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* hardware.h
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*
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* hardware specific header
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#ifndef __AM33XX_HARDWARE_H
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#define __AM33XX_HARDWARE_H
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#include <config.h>
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#include <asm/arch/omap.h>
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#ifdef CONFIG_AM33XX
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#include <asm/arch/hardware_am33xx.h>
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#elif defined(CONFIG_TI816X)
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#include <asm/arch/hardware_ti816x.h>
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#elif defined(CONFIG_TI814X)
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#include <asm/arch/hardware_ti814x.h>
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#elif defined(CONFIG_AM43XX)
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#include <asm/arch/hardware_am43xx.h>
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#endif
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/*
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* Common hardware definitions
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*/
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/* DM Timer base addresses */
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#define DM_TIMER0_BASE 0x4802C000
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#define DM_TIMER1_BASE 0x4802E000
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#define DM_TIMER2_BASE 0x48040000
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#define DM_TIMER3_BASE 0x48042000
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#define DM_TIMER4_BASE 0x48044000
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#define DM_TIMER5_BASE 0x48046000
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#define DM_TIMER6_BASE 0x48048000
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#define DM_TIMER7_BASE 0x4804A000
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/* GPIO Base address */
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#define GPIO0_BASE 0x48032000
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#define GPIO1_BASE 0x4804C000
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/* BCH Error Location Module */
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#define ELM_BASE 0x48080000
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/* EMIF Base address */
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#define EMIF4_0_CFG_BASE 0x4C000000
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#define EMIF4_1_CFG_BASE 0x4D000000
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/* DDR Base address */
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#define DDR_CTRL_ADDR 0x44E10E04
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#define DDR_CONTROL_BASE_ADDR 0x44E11404
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/* UART */
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#if CONFIG_CONS_INDEX == 1
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# define DEFAULT_UART_BASE UART0_BASE
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#elif CONFIG_CONS_INDEX == 2
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# define DEFAULT_UART_BASE UART1_BASE
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#elif CONFIG_CONS_INDEX == 3
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# define DEFAULT_UART_BASE UART2_BASE
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#elif CONFIG_CONS_INDEX == 4
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# define DEFAULT_UART_BASE UART3_BASE
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#elif CONFIG_CONS_INDEX == 5
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# define DEFAULT_UART_BASE UART4_BASE
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#elif CONFIG_CONS_INDEX == 6
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# define DEFAULT_UART_BASE UART5_BASE
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#endif
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/* GPMC Base address */
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#define GPMC_BASE 0x50000000
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/* CPSW Config space */
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#define CPSW_BASE 0x4A100000
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/* Control status register */
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#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
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#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
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#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
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#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
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#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
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#define CTRL_SYSBOOT_15_14_SHIFT 22
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#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
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#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
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#define NUM_CRYSTAL_FREQ 0x4
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int clk_get(int clk);
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#endif /* __AM33XX_HARDWARE_H */
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