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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
260 lines
6.9 KiB
C
260 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/freeze_controller.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/system_manager.h>
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/*
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* Maximum polling loop to wait for IO scan chain engine becomes idle
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* to prevent infinite loop. It is important that this is NOT changed
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* to delay using timer functions, since at the time this function is
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* called, timer might not yet be inited.
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*/
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#define SCANMGR_MAX_DELAY 100
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/*
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* Maximum length of TDI_TDO packet payload is 128 bits,
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* represented by (length - 1) in TDI_TDO header.
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*/
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#define TDI_TDO_MAX_PAYLOAD 127
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#define SCANMGR_STAT_ACTIVE (1 << 31)
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#define SCANMGR_STAT_WFIFOCNT_MASK 0x70000000
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static const struct socfpga_scan_manager *scan_manager_base =
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(void *)(SOCFPGA_SCANMGR_ADDRESS);
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static const struct socfpga_freeze_controller *freeze_controller_base =
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(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
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static struct socfpga_system_manager *sys_mgr_base =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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/**
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* scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
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* @max_iter: Maximum number of iterations to wait for idle
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*
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* Function to check IO scan chain engine status and wait if the engine is
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* is active. Poll the IO scan chain engine till maximum iteration reached.
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*/
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static u32 scan_chain_engine_is_idle(u32 max_iter)
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{
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const u32 mask = SCANMGR_STAT_ACTIVE | SCANMGR_STAT_WFIFOCNT_MASK;
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u32 status;
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/* Poll the engine until the scan engine is inactive. */
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do {
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status = readl(&scan_manager_base->stat);
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if (!(status & mask))
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return 0;
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} while (max_iter--);
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return -ETIMEDOUT;
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}
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#define JTAG_BP_INSN (1 << 0)
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#define JTAG_BP_TMS (1 << 1)
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#define JTAG_BP_PAYLOAD (1 << 2)
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#define JTAG_BP_2BYTE (1 << 3)
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#define JTAG_BP_4BYTE (1 << 4)
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/**
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* scan_mgr_jtag_io() - Access the JTAG chain
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* @flags: Control flags, used to configure the action on the JTAG
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* @iarg: Instruction argument
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* @parg: Payload argument or data
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*
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* Perform I/O on the JTAG chain
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*/
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static void scan_mgr_jtag_io(const u32 flags, const u8 iarg, const u32 parg)
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{
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u32 data = parg;
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if (flags & JTAG_BP_INSN) { /* JTAG instruction */
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/*
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* The SCC JTAG register is LSB first, so make
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* space for the instruction at the LSB.
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*/
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data <<= 8;
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if (flags & JTAG_BP_TMS) {
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data |= (0 << 7); /* TMS instruction. */
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data |= iarg & 0x3f; /* TMS arg is 6 bits. */
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if (flags & JTAG_BP_PAYLOAD)
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data |= (1 << 6);
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} else {
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data |= (1 << 7); /* TDI/TDO instruction. */
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data |= iarg & 0xf; /* TDI/TDO arg is 4 bits. */
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if (flags & JTAG_BP_PAYLOAD)
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data |= (1 << 4);
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}
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}
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if (flags & JTAG_BP_4BYTE)
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writel(data, &scan_manager_base->fifo_quad_byte);
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else if (flags & JTAG_BP_2BYTE)
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writel(data & 0xffff, &scan_manager_base->fifo_double_byte);
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else
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writel(data & 0xff, &scan_manager_base->fifo_single_byte);
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}
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/**
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* scan_mgr_jtag_insn_data() - Send JTAG instruction and data
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* @iarg: Instruction argument
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* @data: Associated data
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* @dlen: Length of data in bits
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*
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* This function is used when programming the IO chains to submit the
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* instruction followed by variable length payload.
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*/
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static int
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scan_mgr_jtag_insn_data(const u8 iarg, const unsigned long *data,
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const unsigned int dlen)
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{
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int i, j;
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scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_2BYTE, iarg, dlen - 1);
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/* 32 bits or more remain */
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for (i = 0; i < dlen / 32; i++)
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scan_mgr_jtag_io(JTAG_BP_4BYTE, 0x0, data[i]);
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if ((dlen % 32) > 24) { /* 31...24 bits remain */
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scan_mgr_jtag_io(JTAG_BP_4BYTE, 0x0, data[i]);
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} else if (dlen % 32) { /* 24...1 bit remain */
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for (j = 0; j < dlen % 32; j += 8)
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scan_mgr_jtag_io(0, 0x0, data[i] >> j);
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}
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return scan_chain_engine_is_idle(SCANMGR_MAX_DELAY);
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}
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/**
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* scan_mgr_io_scan_chain_prg() - Program HPS IO Scan Chain
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* @io_scan_chain_id: IO scan chain ID
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*/
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static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id)
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{
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u32 io_scan_chain_len_in_bits;
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const unsigned long *iocsr_scan_chain;
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unsigned int rem, idx = 0;
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int ret;
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ret = iocsr_get_config_table(io_scan_chain_id, &iocsr_scan_chain,
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&io_scan_chain_len_in_bits);
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if (ret)
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return 1;
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/*
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* De-assert reinit if the IO scan chain is intended for HIO. In
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* this, its the chain 3.
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*/
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if (io_scan_chain_id == 3)
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clrbits_le32(&freeze_controller_base->hioctrl,
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SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
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/*
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* Check if the scan chain engine is inactive and the
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* WFIFO is empty before enabling the IO scan chain
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*/
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ret = scan_chain_engine_is_idle(SCANMGR_MAX_DELAY);
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if (ret)
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return ret;
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/*
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* Enable IO Scan chain based on scan chain id
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* Note: only one chain can be enabled at a time
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*/
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setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
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/* Program IO scan chain. */
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while (io_scan_chain_len_in_bits) {
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if (io_scan_chain_len_in_bits > 128)
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rem = 128;
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else
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rem = io_scan_chain_len_in_bits;
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ret = scan_mgr_jtag_insn_data(0x0, &iocsr_scan_chain[idx], rem);
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if (ret)
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goto error;
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io_scan_chain_len_in_bits -= rem;
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idx += 4;
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}
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/* Disable IO Scan chain when configuration done*/
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clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
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return 0;
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error:
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/* Disable IO Scan chain when error detected */
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clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
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return ret;
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}
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int scan_mgr_configure_iocsr(void)
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{
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int status = 0;
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/* configure the IOCSR through scan chain */
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status |= scan_mgr_io_scan_chain_prg(0);
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status |= scan_mgr_io_scan_chain_prg(1);
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status |= scan_mgr_io_scan_chain_prg(2);
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status |= scan_mgr_io_scan_chain_prg(3);
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return status;
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}
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/**
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* scan_mgr_get_fpga_id() - Obtain FPGA JTAG ID
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*
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* This function obtains JTAG ID from the FPGA TAP controller.
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*/
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u32 scan_mgr_get_fpga_id(void)
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{
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const unsigned long data = 0;
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u32 id = 0xffffffff;
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int ret;
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/* Enable HPS to talk to JTAG in the FPGA through the System Manager */
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writel(0x1, &sys_mgr_base->scanmgrgrp_ctrl);
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/* Enable port 7 */
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writel(0x80, &scan_manager_base->en);
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/* write to CSW to make s2f_ntrst reset */
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writel(0x02, &scan_manager_base->stat);
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/* Add a pause */
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mdelay(1);
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/* write 0x00 to CSW to clear the s2f_ntrst */
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writel(0, &scan_manager_base->stat);
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/*
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* Go to Test-Logic-Reset state.
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* This sets TAP controller into IDCODE mode.
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*/
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scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_TMS, 0x1f | (1 << 5), 0x0);
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/* Go to Run-Test/Idle -> DR-Scan -> Capture-DR -> Shift-DR state. */
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scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_TMS, 0x02 | (1 << 4), 0x0);
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/*
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* Push 4 bytes of data through TDI->DR->TDO.
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*
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* Length of TDI data is 32bits (length - 1) and they are only
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* zeroes as we care only for TDO data.
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*/
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ret = scan_mgr_jtag_insn_data(0x4, &data, 32);
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/* Read 32 bit from captured JTAG data. */
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if (!ret)
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id = readl(&scan_manager_base->fifo_quad_byte);
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/* Disable all port */
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writel(0, &scan_manager_base->en);
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writel(0, &sys_mgr_base->scanmgrgrp_ctrl);
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return id;
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}
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