mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 05:36:17 +09:00
5da627a424
- Add support for Altera FPGA ACEX1K
* Patches by Thomas Lange, 09 Oct 2003:
- Endian swap ATA identity for all big endian CPUs, not just PPC
- MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
args to linux
- add support for dbau1x00 board (MIPS32)
119 lines
1.9 KiB
ArmAsm
119 lines
1.9 KiB
ArmAsm
/* Memory sub-system initialization code */
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#include <asm/au1x00.h>
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.globl memsetup
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memsetup:
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/* First setup pll:s to make serial work ok */
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/* We have a 12 MHz crystal */
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li t0, SYS_CPUPLL
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li t1, 0x21 /* 396 MHz */
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sw t1, 0(t0)
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sync
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nop
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/* Setup AUX PLL */
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li t0, SYS_AUXPLL
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li t1, 8 /* 96 MHz */
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sw t1, 0(t0) /* aux pll */
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sync
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/* SDCS 0,1 SDRAM */
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li t0, MEM_SDMODE0
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li t1, 0x005522AA
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sw t1, 0(t0)
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li t0, MEM_SDMODE1
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li t1, 0x005522AA
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sw t1, 0(t0)
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li t0, MEM_SDADDR0
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li t1, 0x001003F8
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sw t1, 0(t0)
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li t0, MEM_SDADDR1
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li t1, 0x001023F8
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sw t1, 0(t0)
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sync
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li t0, MEM_SDREFCFG
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li t1, 0x64000C24 /* Disable */
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sw t1, 0(t0)
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sync
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li t0, MEM_SDPRECMD
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sw zero, 0(t0)
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sync
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li t0, MEM_SDAUTOREF
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sw zero, 0(t0)
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sync
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sw zero, 0(t0)
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sync
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li t0, MEM_SDREFCFG
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li t1, 0x66000C24 /* Enable */
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD0
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li t1, 0x00000033
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD1
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li t1, 0x00000033
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sw t1, 0(t0)
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sync
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/* Static memory controller */
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/* RCE0 AMD 29LV640M MirrorBit Flash */
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li t0, MEM_STCFG0
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li t1, 0x00000003
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sw t1, 0(t0)
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li t0, MEM_STTIME0
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li t1, 0x22080b20
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sw t1, 0(t0)
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li t0, MEM_STADDR0
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li t1, 0x11E03F80
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sw t1, 0(t0)
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/* RCE1 CPLD Board Logic */
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li t0, MEM_STCFG1
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li t1, 0x00000080
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sw t1, 0(t0)
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li t0, MEM_STTIME1
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li t1, 0x22080a20
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sw t1, 0(t0)
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li t0, MEM_STADDR1
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li t1, 0x10c03f00
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sw t1, 0(t0)
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/* RCE3 PCMCIA 250ns */
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li t0, MEM_STCFG3
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li t1, 0x00000002
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sw t1, 0(t0)
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li t0, MEM_STTIME3
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li t1, 0x280E3E07
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sw t1, 0(t0)
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li t0, MEM_STADDR3
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li t1, 0x10000000
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sw t1, 0(t0)
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sync
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j ra
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nop
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