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https://github.com/brain-hackers/u-boot-brain
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896720ceb2
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0. This decreases data burst rate with which data packets are posted from the TX latency FIFO to compensate for latencies in DDR pipeline during DMA. This avoids Tx buffer underruns and leads to successful usb writes Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
157 lines
3.9 KiB
C
157 lines
3.9 KiB
C
/*
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* (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
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*
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* Author: Tor Krill tor@excito.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <usb/ehci-fsl.h>
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#include <hwconfig.h>
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#include <asm/fsl_errata.h>
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#include "ehci.h"
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static void set_txfifothresh(struct usb_ehci *, u32);
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/* Check USB PHY clock valid */
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static int usb_phy_clk_valid(struct usb_ehci *ehci)
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{
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if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
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in_be32(&ehci->prictrl))) {
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printf("USB PHY clock invalid!\n");
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return 0;
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} else {
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return 1;
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}
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}
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/*
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* Create the appropriate control structures to manage
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* a new EHCI host controller.
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*
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* Excerpts from linux ehci fsl driver.
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*/
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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struct usb_ehci *ehci = NULL;
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const char *phy_type = NULL;
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size_t len;
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char current_usb_controller[5];
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#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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char usb_phy[5];
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usb_phy[0] = '\0';
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#endif
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if (has_erratum_a007075()) {
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/*
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* A 5ms delay is needed after applying soft-reset to the
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* controller to let external ULPI phy come out of reset.
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* This delay needs to be added before re-initializing
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* the controller after soft-resetting completes
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*/
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mdelay(5);
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}
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memset(current_usb_controller, '\0', 5);
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snprintf(current_usb_controller, 4, "usb%d", index+1);
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switch (index) {
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case 0:
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ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
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break;
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case 1:
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ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
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break;
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default:
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printf("ERROR: wrong controller index!!\n");
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break;
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};
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*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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/* Set to Host mode */
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setbits_le32(&ehci->usbmode, CM_HOST);
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out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
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out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
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/* Init phy */
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if (hwconfig_sub(current_usb_controller, "phy_type"))
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phy_type = hwconfig_subarg(current_usb_controller,
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"phy_type", &len);
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else
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phy_type = getenv("usb_phy_type");
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if (!phy_type) {
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#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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/* if none specified assume internal UTMI */
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strcpy(usb_phy, "utmi");
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phy_type = usb_phy;
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#else
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printf("WARNING: USB phy type not defined !!\n");
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return -1;
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#endif
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}
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if (!strncmp(phy_type, "utmi", 4)) {
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#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
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setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
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setbits_be32(&ehci->control, UTMI_PHY_EN);
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udelay(1000); /* delay required for PHY Clk to appear */
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#endif
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out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
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setbits_be32(&ehci->control, USB_EN);
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} else {
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setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
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clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
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udelay(1000); /* delay required for PHY Clk to appear */
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if (!usb_phy_clk_valid(ehci))
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return -EINVAL;
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out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
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}
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out_be32(&ehci->prictrl, 0x0000000c);
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out_be32(&ehci->age_cnt_limit, 0x00000040);
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out_be32(&ehci->sictrl, 0x00000001);
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in_le32(&ehci->usbmode);
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if (SVR_SOC_VER(get_svr()) == SVR_T4240 &&
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IS_SVR_REV(get_svr(), 2, 0))
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set_txfifothresh(ehci, TXFIFOTHRESH);
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the the EHCI host controller.
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*/
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int ehci_hcd_stop(int index)
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{
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return 0;
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}
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/*
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* Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
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* to counter DDR latencies in writing data into Tx buffer.
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* This prevents Tx buffer from getting underrun
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*/
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static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
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{
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u32 cmd;
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cmd = ehci_readl(&ehci->txfilltuning);
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cmd &= ~TXFIFO_THRESH_MASK;
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cmd |= TXFIFO_THRESH(txfifo_thresh);
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ehci_writel(&ehci->txfilltuning, cmd);
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}
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