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https://github.com/brain-hackers/u-boot-brain
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1630853085
With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot. At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed. Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration. Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix. Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
160 lines
3.8 KiB
C
160 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Primary-to-Sideband Bridge
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*
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* Copyright 2019 Google LLC
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*/
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#define LOG_CATEGORY UCLASS_P2SB
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <p2sb.h>
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#include <spl.h>
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#include <asm/pci.h>
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struct p2sb_platdata {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_intel_p2sb dtplat;
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#endif
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ulong mmio_base;
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pci_dev_t bdf;
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};
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/* PCI config space registers */
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#define HPTC_OFFSET 0x60
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#define HPTC_ADDR_ENABLE_BIT BIT(7)
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/* High Performance Event Timer Configuration */
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#define P2SB_HPTC 0x60
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#define P2SB_HPTC_ADDRESS_ENABLE BIT(7)
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/*
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* ADDRESS_SELECT ENCODING_RANGE
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* 0 0xfed0 0000 - 0xfed0 03ff
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* 1 0xfed0 1000 - 0xfed0 13ff
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* 2 0xfed0 2000 - 0xfed0 23ff
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* 3 0xfed0 3000 - 0xfed0 33ff
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*/
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#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
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#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
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#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
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#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
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/*
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* p2sb_early_init() - Enable decoding for HPET range
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*
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* This is needed by FSP-M which uses the High Precision Event Timer.
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*
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* @dev: P2SB device
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* @return 0 if OK, -ve on error
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*/
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static int p2sb_early_init(struct udevice *dev)
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{
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struct p2sb_platdata *plat = dev_get_platdata(dev);
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pci_dev_t pdev = plat->bdf;
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/*
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* Enable decoding for HPET memory address range.
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* HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
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* the High Performance Timer memory address range
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* selected by bits 1:0
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*/
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pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
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PCI_SIZE_8);
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/* Enable PCR Base address in PCH */
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pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
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PCI_SIZE_32);
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pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
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/* Enable P2SB MSE */
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pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY, PCI_SIZE_8);
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return 0;
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}
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static int p2sb_spl_init(struct udevice *dev)
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{
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/* Enable decoding for HPET. Needed for FSP global pointer storage */
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dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
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P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
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return 0;
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}
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int p2sb_ofdata_to_platdata(struct udevice *dev)
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{
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struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
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struct p2sb_platdata *plat = dev_get_platdata(dev);
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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int ret;
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u32 base[2];
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ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
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if (ret)
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return log_msg_ret("Missing/short early-regs", ret);
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plat->mmio_base = base[0];
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/* TPL sets up the initial BAR */
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if (spl_phase() == PHASE_TPL) {
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plat->bdf = pci_get_devfn(dev);
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if (plat->bdf < 0)
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return log_msg_ret("Cannot get p2sb PCI address",
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plat->bdf);
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}
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upriv->mmio_base = plat->mmio_base;
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#else
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plat->mmio_base = plat->dtplat.early_regs[0];
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plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
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upriv->mmio_base = plat->mmio_base;
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#endif
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return 0;
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}
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static int p2sb_probe(struct udevice *dev)
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{
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if (spl_phase() == PHASE_TPL)
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return p2sb_early_init(dev);
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else if (spl_phase() == PHASE_SPL)
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return p2sb_spl_init(dev);
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return 0;
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}
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static int p2sb_child_post_bind(struct udevice *dev)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
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int ret;
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u32 pid;
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ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
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if (ret)
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return ret;
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pplat->pid = pid;
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#endif
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return 0;
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}
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static const struct udevice_id p2sb_ids[] = {
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{ .compatible = "intel,p2sb" },
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{ }
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};
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U_BOOT_DRIVER(p2sb_drv) = {
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.name = "intel_p2sb",
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.id = UCLASS_P2SB,
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.of_match = p2sb_ids,
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.probe = p2sb_probe,
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.ofdata_to_platdata = p2sb_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
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.per_child_platdata_auto_alloc_size =
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sizeof(struct p2sb_child_platdata),
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.child_post_bind = p2sb_child_post_bind,
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};
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