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https://github.com/brain-hackers/u-boot-brain
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d496162c85
Most x86 CPUs use a mechanism where the SPI flash is mapped into the very top of 32-bit address space, so that it can be executed in place and read simply by copying from memory. For an 8MB ROM the mapping starts at 0xff800000. However some recent Intel CPUs do not use a simple 1:1 memory map. Instead the map starts at a different address and not all of the SPI flash is accessible through the map. This 'Fast SPI' feature requires that U-Boot check the location of the map. It is also possible (optionally) to read from the SPI flash using a driver. Add support for booting from Fast SPI. The memory-mapped version is used by both TPL and SPL on Apollo Lake. In respect of a SPI flash driver, the actual SPI driver is ich.c - this just adds a few helper functions and definitions. This is used by Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Google LLC
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/cpu_common.h>
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#include <asm/fast_spi.h>
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#include <asm/pci.h>
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/*
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* Returns bios_start and fills in size of the BIOS region.
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*/
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static ulong fast_spi_get_bios_region(struct fast_spi_regs *regs,
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uint *bios_size)
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{
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ulong bios_start, bios_end;
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/*
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* BIOS_BFPREG provides info about BIOS-Flash Primary Region Base and
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* Limit. Base and Limit fields are in units of 4K.
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*/
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u32 val = readl(®s->bfp);
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bios_start = (val & SPIBAR_BFPREG_PRB_MASK) << 12;
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bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
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SPIBAR_BFPREG_PRL_SHIFT) + 1) << 12;
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*bios_size = bios_end - bios_start;
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return bios_start;
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}
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int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep,
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uint *offsetp)
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{
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struct fast_spi_regs *regs;
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ulong bar, base, mmio_base;
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/* Special case to find mapping without probing the device */
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pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32);
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mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK;
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regs = (struct fast_spi_regs *)mmio_base;
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base = fast_spi_get_bios_region(regs, map_sizep);
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*map_basep = (u32)-*map_sizep - base;
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*offsetp = base;
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return 0;
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}
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int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base)
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{
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/* Program Temporary BAR for SPI */
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pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0,
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mmio_base | PCI_BASE_ADDRESS_SPACE_MEMORY,
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PCI_SIZE_32);
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/* Enable Bus Master and MMIO Space */
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pci_x86_clrset_config(pdev, PCI_COMMAND, 0, PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY, PCI_SIZE_8);
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/*
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* Disable the BIOS write protect so write commands are allowed.
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* Enable Prefetching and caching.
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*/
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pci_x86_clrset_config(pdev, SPIBAR_BIOS_CONTROL,
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SPIBAR_BIOS_CONTROL_EISS |
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SPIBAR_BIOS_CONTROL_CACHE_DISABLE,
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SPIBAR_BIOS_CONTROL_WPD |
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SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE, PCI_SIZE_8);
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return 0;
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}
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