mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-30 14:53:44 +09:00
2cf0eb5dfd
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
73 lines
1.4 KiB
Plaintext
73 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* T2080/T2081 Silicon/SoC Device Tree Source (pre include)
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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* Copyright 2018 NXP
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*/
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/dts-v1/;
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/include/ "e6500_power_isa.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: PowerPC,e6500@0 {
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device_type = "cpu";
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reg = <0 1>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu1: PowerPC,e6500@2 {
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device_type = "cpu";
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reg = <2 3>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu2: PowerPC,e6500@4 {
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device_type = "cpu";
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reg = <4 5>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu3: PowerPC,e6500@6 {
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device_type = "cpu";
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reg = <6 7>;
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fsl,portid-mapping = <0x80000000>;
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};
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <4>;
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reg = <0x40000 0x40000>;
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compatible = "fsl,mpic";
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device_type = "open-pic";
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clock-frequency = <0x0>;
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};
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esdhc: esdhc@114000 {
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compatible = "fsl,esdhc";
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reg = <0x114000 0x1000>;
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interrupts = <48 2 0 0>;
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clock-frequency = <0>;
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sdhci,auto-cmd12;
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bus-width = <4>;
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voltage-ranges = <1800 1800 3300 3300>;
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};
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};
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};
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