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https://github.com/brain-hackers/u-boot-brain
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![]() * Boot failures have been discovered due to a combination of routing issues and non optimal ddr3 timings in the EMIF * Since ddr3 timings are different after significant board layout changes different timings are required for alpha, beta and production boards. Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com> |
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cpu | ||
dts | ||
imx-common | ||
include/asm | ||
lib | ||
config.mk |