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![Simon Glass](/assets/img/avatar_default.png)
The memory and silicon init parts of the FSP need support code to work. Add this for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
211 lines
5.9 KiB
C
211 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Google LLC
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/fsp/fsp_configs.h>
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#include <asm/arch/fsp/fsp_m_upd.h>
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#include <asm/fsp2/fsp_internal.h>
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#include <dm/uclass-internal.h>
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/*
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* ODT settings:
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* If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B,
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* choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A
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* and LOW for ODT_B, choose ODT_A_B_HIGH_LOW.
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*
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* Note that the enum values correspond to the interpreted UPD fields
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* within Ch[3:0]_OdtConfig parameters.
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*/
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enum {
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ODT_A_B_HIGH_LOW = 0 << 1,
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ODT_A_B_HIGH_HIGH = 1 << 1,
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N_WR_24 = 1 << 5,
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};
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/*
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* LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
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* There are four physical LPDDR4 channels, each 32-bits wide. There are two
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* logical channels using two physical channels together to form a 64-bit
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* interface to memory for each logical channel.
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*/
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enum {
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LP4_PHYS_CH0A,
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LP4_PHYS_CH0B,
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LP4_PHYS_CH1A,
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LP4_PHYS_CH1B,
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LP4_NUM_PHYS_CHANNELS,
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};
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/*
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* The DQs within a physical channel can be bit-swizzled within each byte.
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* Within a channel the bytes can be swapped, but the DQs need to be routed
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* with the corresponding DQS (strobe).
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*/
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enum {
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LP4_DQS0,
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LP4_DQS1,
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LP4_DQS2,
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LP4_DQS3,
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LP4_NUM_BYTE_LANES,
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DQ_BITS_PER_DQS = 8,
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};
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/* Provide bit swizzling per DQS and byte swapping within a channel */
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struct lpddr4_chan_swizzle_cfg {
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u8 dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS];
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};
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struct lpddr4_swizzle_cfg {
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struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
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};
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static void setup_sdram(struct fsp_m_config *cfg,
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const struct lpddr4_swizzle_cfg *swizzle_cfg)
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{
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const struct lpddr4_chan_swizzle_cfg *sch;
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/* Number of bytes to copy per DQS */
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const size_t sz = DQ_BITS_PER_DQS;
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int chan;
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cfg->memory_down = 1;
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cfg->scrambler_support = 1;
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cfg->channel_hash_mask = 0x36;
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cfg->slice_hash_mask = 9;
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cfg->interleaved_mode = 2;
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cfg->channels_slices_enable = 0;
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cfg->min_ref_rate2x_enable = 0;
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cfg->dual_rank_support_enable = 1;
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/* LPDDR4 is memory down so no SPD addresses */
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cfg->dimm0_spd_address = 0;
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cfg->dimm1_spd_address = 0;
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for (chan = 0; chan < 4; chan++) {
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struct fsp_ram_channel *ch = &cfg->chan[chan];
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ch->rank_enable = 1;
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ch->device_width = 1;
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ch->dram_density = 2;
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ch->option = 3;
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ch->odt_config = ODT_A_B_HIGH_HIGH;
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}
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/*
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* CH0_DQB byte lanes in the bit swizzle configuration field are
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* not 1:1. The mapping within the swizzling field is:
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* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
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* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
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* indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
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* indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
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*/
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sch = &swizzle_cfg->phys[LP4_PHYS_CH0B];
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memcpy(&cfg->ch_bit_swizzling[0][0], &sch->dqs[LP4_DQS1], sz);
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memcpy(&cfg->ch_bit_swizzling[0][8], &sch->dqs[LP4_DQS0], sz);
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memcpy(&cfg->ch_bit_swizzling[0][16], &sch->dqs[LP4_DQS3], sz);
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memcpy(&cfg->ch_bit_swizzling[0][24], &sch->dqs[LP4_DQS2], sz);
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/*
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* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
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*/
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sch = &swizzle_cfg->phys[LP4_PHYS_CH0A];
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memcpy(&cfg->ch_bit_swizzling[1][0], &sch->dqs[LP4_DQS0], sz);
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memcpy(&cfg->ch_bit_swizzling[1][8], &sch->dqs[LP4_DQS1], sz);
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memcpy(&cfg->ch_bit_swizzling[1][16], &sch->dqs[LP4_DQS2], sz);
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memcpy(&cfg->ch_bit_swizzling[1][24], &sch->dqs[LP4_DQS3], sz);
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sch = &swizzle_cfg->phys[LP4_PHYS_CH1B];
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memcpy(&cfg->ch_bit_swizzling[2][0], &sch->dqs[LP4_DQS1], sz);
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memcpy(&cfg->ch_bit_swizzling[2][8], &sch->dqs[LP4_DQS0], sz);
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memcpy(&cfg->ch_bit_swizzling[2][16], &sch->dqs[LP4_DQS3], sz);
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memcpy(&cfg->ch_bit_swizzling[2][24], &sch->dqs[LP4_DQS2], sz);
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/*
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* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
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*/
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sch = &swizzle_cfg->phys[LP4_PHYS_CH1A];
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memcpy(&cfg->ch_bit_swizzling[3][0], &sch->dqs[LP4_DQS0], sz);
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memcpy(&cfg->ch_bit_swizzling[3][8], &sch->dqs[LP4_DQS1], sz);
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memcpy(&cfg->ch_bit_swizzling[3][16], &sch->dqs[LP4_DQS2], sz);
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memcpy(&cfg->ch_bit_swizzling[3][24], &sch->dqs[LP4_DQS3], sz);
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}
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int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
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{
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struct fsp_m_config *cfg = &upd->config;
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struct fspm_arch_upd *arch = &upd->arch;
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arch->nvs_buffer_ptr = NULL;
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prepare_mrc_cache(upd);
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arch->stack_base = (void *)0xfef96000;
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arch->boot_loader_tolum_size = 0;
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arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION;
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cfg->serial_debug_port_type = 2;
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cfg->serial_debug_port_device = 2;
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cfg->serial_debug_port_stride_size = 2;
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cfg->serial_debug_port_address = 0;
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cfg->package = 1;
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/* Don't enforce a memory size limit */
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cfg->memory_size_limit = 0;
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cfg->low_memory_max_value = 2048; /* 2 GB */
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/* No restrictions on memory above 4GiB */
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cfg->high_memory_max_value = 0;
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/* Always default to attempt to use saved training data */
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cfg->disable_fast_boot = 0;
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const u8 *swizzle_data;
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swizzle_data = dev_read_u8_array_ptr(dev, "lpddr4-swizzle",
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LP4_NUM_BYTE_LANES *
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DQ_BITS_PER_DQS *
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LP4_NUM_PHYS_CHANNELS);
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if (!swizzle_data)
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return log_msg_ret("Cannot read swizzel data", -EINVAL);
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setup_sdram(cfg, (struct lpddr4_swizzle_cfg *)swizzle_data);
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cfg->pre_mem_gpio_table_ptr = 0;
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cfg->profile = 0xb;
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cfg->msg_level_mask = 0;
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/* other */
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cfg->skip_cse_rbp = 1;
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cfg->periodic_retraining_disable = 0;
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cfg->enable_s3_heci2 = 0;
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return 0;
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}
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/*
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* The FSP-M binary appears to break the SPI controller. It can be fixed by
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* writing the BAR again, so do that here
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*/
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int fspm_done(struct udevice *dev)
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{
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struct udevice *spi;
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int ret;
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/* Don't probe the device, since that reads the BAR */
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ret = uclass_find_first_device(UCLASS_SPI, &spi);
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if (ret)
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return log_msg_ret("SPI", ret);
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if (!spi)
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return log_msg_ret("no SPI", -ENODEV);
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dm_pci_write_config32(spi, PCI_BASE_ADDRESS_0,
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IOMAP_SPI_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY);
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return 0;
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}
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