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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
207 lines
4.7 KiB
C
207 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/sdram.h>
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#include <asm/arch-rockchip/sdram_pctl_px30.h>
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#include <linux/delay.h>
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/*
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* rank = 1: cs0
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* rank = 2: cs1
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*/
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void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num)
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{
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writel((rank << 4) | (1 << 0), pctl_base + DDR_PCTL2_MRCTRL0);
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writel((mr_num << 8), pctl_base + DDR_PCTL2_MRCTRL1);
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setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
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while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
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continue;
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while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
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continue;
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}
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/* rank = 1: cs0
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* rank = 2: cs1
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* rank = 3: cs0 & cs1
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* note: be careful of keep mr original val
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*/
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int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
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u32 dramtype)
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{
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while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
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continue;
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if (dramtype == DDR3 || dramtype == DDR4) {
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writel((mr_num << 12) | (rank << 4) | (0 << 0),
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pctl_base + DDR_PCTL2_MRCTRL0);
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writel(arg, pctl_base + DDR_PCTL2_MRCTRL1);
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} else {
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writel((rank << 4) | (0 << 0),
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pctl_base + DDR_PCTL2_MRCTRL0);
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writel((mr_num << 8) | (arg & 0xff),
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pctl_base + DDR_PCTL2_MRCTRL1);
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}
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setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
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while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
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continue;
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while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
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continue;
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return 0;
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}
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/*
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* rank : 1:cs0, 2:cs1, 3:cs0&cs1
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* vrefrate: 4500: 45%,
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*/
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int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
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u32 dramtype)
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{
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u32 tccd_l, value;
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u32 dis_auto_zq = 0;
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if (dramtype != DDR4 || vrefrate < 4500 ||
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vrefrate > 9200)
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return (-1);
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tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf;
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tccd_l = (tccd_l - 4) << 10;
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if (vrefrate > 7500) {
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/* range 1 */
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value = ((vrefrate - 6000) / 65) | tccd_l;
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} else {
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/* range 2 */
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value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6);
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}
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dis_auto_zq = pctl_dis_zqcs_aref(pctl_base);
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/* enable vrefdq calibratin */
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pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype);
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udelay(1);/* tvrefdqe */
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/* write vrefdq value */
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pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype);
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udelay(1);/* tvref_time */
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pctl_write_mr(pctl_base, rank, 6, value | (0 << 7), dramtype);
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udelay(1);/* tvrefdqx */
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pctl_rest_zqcs_aref(pctl_base, dis_auto_zq);
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return 0;
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}
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static int upctl2_update_ref_reg(void __iomem *pctl_base)
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{
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u32 ret;
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ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1);
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writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3);
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return 0;
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}
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u32 pctl_dis_zqcs_aref(void __iomem *pctl_base)
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{
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u32 dis_auto_zq = 0;
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/* disable zqcs */
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if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
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(1ul << 31))) {
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dis_auto_zq = 1;
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setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
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}
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/* disable auto refresh */
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setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
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upctl2_update_ref_reg(pctl_base);
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return dis_auto_zq;
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}
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void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq)
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{
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/* restore zqcs */
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if (dis_auto_zq)
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clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
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/* restore auto refresh */
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clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
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upctl2_update_ref_reg(pctl_base);
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}
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u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs,
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struct sdram_cap_info *cap_info,
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u32 dram_type)
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{
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u32 tmp = 0, tmp_adr = 0, i;
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for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) {
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if (pctl_regs->pctl[i][0] == 0) {
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tmp = pctl_regs->pctl[i][1];/* MSTR */
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tmp_adr = i;
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}
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}
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tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12));
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switch (cap_info->dbw) {
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case 2:
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tmp |= (3ul << 30);
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break;
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case 1:
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tmp |= (2ul << 30);
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break;
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case 0:
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default:
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tmp |= (1ul << 30);
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break;
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}
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/*
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* If DDR3 or DDR4 MSTR.active_ranks=1,
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* it will gate memory clock when enter power down.
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* Force set active_ranks to 3 to workaround it.
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*/
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if (cap_info->rank == 2 || dram_type == DDR3 ||
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dram_type == DDR4)
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tmp |= 3 << 24;
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else
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tmp |= 1 << 24;
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tmp |= (2 - cap_info->bw) << 12;
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pctl_regs->pctl[tmp_adr][1] = tmp;
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return 0;
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}
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int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs,
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u32 sr_idle, u32 pd_idle)
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{
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u32 i;
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for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) {
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writel(pctl_regs->pctl[i][1],
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pctl_base + pctl_regs->pctl[i][0]);
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}
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clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG,
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(0xff << 16) | 0x1f,
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((sr_idle & 0xff) << 16) | (pd_idle & 0x1f));
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clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL,
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0xfff << 16,
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5 << 16);
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/* disable zqcs */
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setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31);
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return 0;
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}
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