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https://github.com/brain-hackers/u-boot-brain
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2c17e6d1d9
GPMC controller is common IP to interface with both NAND and NOR flash devices. Also, it supports max 8 chip-selects, which can be independently connected to any of the devices. But ROM code expects the boot-device to be connected to only chip-select[0]. Thus to resolve conflict between NOR and NAND boot. This patch: - combines NOR and NAND configs spread in board files to common gpmc_init() - configures GPMC based on boot-mode selected for SPL boot. Signed-off-by: Pekon Gupta <pekon@ti.com> |
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.. | ||
board.c | ||
clock_am33xx.c | ||
clock_am43xx.c | ||
clock_ti814x.c | ||
clock_ti816x.c | ||
clock.c | ||
config.mk | ||
ddr.c | ||
emif4.c | ||
Makefile | ||
mem.c | ||
mux.c | ||
sys_info.c | ||
u-boot-spl.lds |