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![David Brownell](/assets/img/avatar_default.png)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
246 lines
6.8 KiB
C
246 lines
6.8 KiB
C
/*
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* NAND driver for TI DaVinci based boards.
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Based on Linux DaVinci NAND driver by TI. Original copyright follows:
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*/
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/*
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*
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* linux/drivers/mtd/nand/nand_davinci.c
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*
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* NAND Flash Driver
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*
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* Overview:
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* This is a device driver for the NAND flash device found on the
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* DaVinci board which utilizes the Samsung k9k2g08 part.
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*
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Modifications:
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ver. 1.0: Feb 2005, Vinod/Sudhakar
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-
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <asm/arch/nand_defs.h>
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#include <asm/arch/emif_defs.h>
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static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
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static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
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IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
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if (ctrl & NAND_CTRL_CHANGE) {
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if ( ctrl & NAND_CLE )
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IO_ADDR_W |= MASK_CLE;
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if ( ctrl & NAND_ALE )
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IO_ADDR_W |= MASK_ALE;
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this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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#ifdef CONFIG_SYS_NAND_HW_ECC
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static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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int dummy;
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dummy = emif_regs->NANDF1ECC;
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/* FIXME: only chipselect 0 is supported for now */
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emif_regs->NANDFCR |= 1 << 8;
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}
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static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
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{
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u_int32_t ecc = 0;
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if (region == 1)
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ecc = emif_regs->NANDF1ECC;
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else if (region == 2)
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ecc = emif_regs->NANDF2ECC;
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else if (region == 3)
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ecc = emif_regs->NANDF3ECC;
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else if (region == 4)
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ecc = emif_regs->NANDF4ECC;
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return(ecc);
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}
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static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
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{
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u_int32_t tmp;
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const int region = 1;
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tmp = nand_davinci_readecc(mtd, region);
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/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
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* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
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tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
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/* Invert so that erased block ECC is correct */
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tmp = ~tmp;
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*ecc_code++ = tmp;
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*ecc_code++ = tmp >> 8;
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*ecc_code++ = tmp >> 16;
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/* NOTE: the above code matches mainline Linux:
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* .PQR.stu ==> ~PQRstu
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*
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* MontaVista/TI kernels encode those bytes differently, use
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* complicated (and allegedly sometimes-wrong) correction code,
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* and usually shipped with U-Boot that uses software ECC:
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* .PQR.stu ==> PsQRtu
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*
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* If you need MV/TI compatible NAND I/O in U-Boot, it should
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* be possible to (a) change the mangling above, (b) reverse
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* that mangling in nand_davinci_correct_data() below.
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*/
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return 0;
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}
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static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
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{
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struct nand_chip *this = mtd->priv;
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u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
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(read_ecc[2] << 16);
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u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
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(calc_ecc[2] << 16);
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u_int32_t diff = ecc_calc ^ ecc_nand;
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if (diff) {
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if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
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/* Correctable error */
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if ((diff >> (12 + 3)) < this->ecc.size) {
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uint8_t find_bit = 1 << ((diff >> 12) & 7);
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uint32_t find_byte = diff >> (12 + 3);
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dat[find_byte] ^= find_bit;
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MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
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"bit ECC error at offset: %d, bit: "
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"%d\n", find_byte, find_bit);
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return 1;
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} else {
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return -1;
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}
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} else if (!(diff & (diff - 1))) {
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/* Single bit ECC error in the ECC itself,
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nothing to fix */
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MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
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"ECC.\n");
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return 1;
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} else {
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/* Uncorrectable error */
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MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
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return -1;
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}
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}
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return(0);
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}
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#endif /* CONFIG_SYS_NAND_HW_ECC */
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static int nand_davinci_dev_ready(struct mtd_info *mtd)
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{
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return emif_regs->NANDFSR & 0x1;
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}
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static void nand_flash_init(void)
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{
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/* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
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* Instead, have your board_init() set EMIF timings, based on its
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* knowledge of the clocks and what devices are hooked up ... and
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* don't even do that unless no UBL handled it.
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*/
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#ifdef CONFIG_SOC_DM644X
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u_int32_t acfg1 = 0x3ffffffc;
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/*------------------------------------------------------------------*
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* NAND FLASH CHIP TIMEOUT @ 459 MHz *
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* *
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* AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
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* AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
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* *
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*------------------------------------------------------------------*/
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acfg1 = 0
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| (0 << 31 ) /* selectStrobe */
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| (0 << 30 ) /* extWait */
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| (1 << 26 ) /* writeSetup 10 ns */
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| (3 << 20 ) /* writeStrobe 40 ns */
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| (1 << 17 ) /* writeHold 10 ns */
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| (1 << 13 ) /* readSetup 10 ns */
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| (5 << 7 ) /* readStrobe 60 ns */
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| (1 << 4 ) /* readHold 10 ns */
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| (3 << 2 ) /* turnAround ?? ns */
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| (0 << 0 ) /* asyncSize 8-bit bus */
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;
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emif_regs->AB1CR = acfg1; /* CS2 */
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emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
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#endif
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}
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void davinci_nand_init(struct nand_chip *nand)
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{
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nand->chip_delay = 0;
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#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
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nand->options = NAND_USE_FLASH_BBT;
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#endif
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#ifdef CONFIG_SYS_NAND_HW_ECC
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.size = 512;
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nand->ecc.bytes = 3;
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nand->ecc.calculate = nand_davinci_calculate_ecc;
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nand->ecc.correct = nand_davinci_correct_data;
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nand->ecc.hwctl = nand_davinci_enable_hwecc;
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#else
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nand->ecc.mode = NAND_ECC_SOFT;
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#endif /* CONFIG_SYS_NAND_HW_ECC */
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/* Set address of hardware control function */
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nand->cmd_ctrl = nand_davinci_hwcontrol;
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nand->dev_ready = nand_davinci_dev_ready;
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nand_flash_init();
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}
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int board_nand_init(struct nand_chip *chip) __attribute__((weak));
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int board_nand_init(struct nand_chip *chip)
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{
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davinci_nand_init(chip);
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return 0;
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}
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