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![Simon Goldschmidt](/assets/img/avatar_default.png)
As a preparation for merging the socfpga gen5 devicetree files from Linux, this patch makes the dwapb gpio driver work correctly without the 'bank-name' property on the gpio-controller nodes. This property is not present in the Linux drivers and thus is not present in the Linux devicetrees. It is only used to access pins via bank name. This fallback is necessary since without it, the driver will return an error code which will lead to an error in U-Boot startup. The bank names will still be added to the default board device trees in follow-up patch, but other boards using this driver and not including the bank name should also work with the socfpga.dtsi without adding the bank-name property. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
229 lines
5.2 KiB
C
229 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015 Marek Vasut <marex@denx.de>
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*
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* DesignWare APB GPIO driver
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/root.h>
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#include <errno.h>
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#include <reset.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GPIO_SWPORT_DR(p) (0x00 + (p) * 0xc)
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#define GPIO_SWPORT_DDR(p) (0x04 + (p) * 0xc)
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#define GPIO_INTEN 0x30
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#define GPIO_INTMASK 0x34
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#define GPIO_INTTYPE_LEVEL 0x38
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#define GPIO_INT_POLARITY 0x3c
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#define GPIO_INTSTATUS 0x40
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#define GPIO_PORTA_DEBOUNCE 0x48
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#define GPIO_PORTA_EOI 0x4c
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#define GPIO_EXT_PORT(p) (0x50 + (p) * 4)
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struct gpio_dwapb_priv {
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struct reset_ctl_bulk resets;
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};
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struct gpio_dwapb_platdata {
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const char *name;
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int bank;
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int pins;
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fdt_addr_t base;
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};
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static int dwapb_gpio_direction_input(struct udevice *dev, unsigned pin)
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{
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struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
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clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
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return 0;
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}
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static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin,
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int val)
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{
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struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
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setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
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if (val)
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setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
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else
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clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
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return 0;
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}
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static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin)
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{
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struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
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return !!(readl(plat->base + GPIO_EXT_PORT(plat->bank)) & (1 << pin));
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}
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static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val)
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{
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struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
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if (val)
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setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
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else
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clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
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return 0;
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}
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static int dwapb_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
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u32 gpio;
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gpio = readl(plat->base + GPIO_SWPORT_DDR(plat->bank));
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if (gpio & BIT(offset))
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static const struct dm_gpio_ops gpio_dwapb_ops = {
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.direction_input = dwapb_gpio_direction_input,
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.direction_output = dwapb_gpio_direction_output,
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.get_value = dwapb_gpio_get_value,
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.set_value = dwapb_gpio_set_value,
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.get_function = dwapb_gpio_get_function,
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};
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static int gpio_dwapb_reset(struct udevice *dev)
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{
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int ret;
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struct gpio_dwapb_priv *priv = dev_get_priv(dev);
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ret = reset_get_bulk(dev, &priv->resets);
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if (ret) {
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/* Return 0 if error due to !CONFIG_DM_RESET and reset
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* DT property is not present.
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*/
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if (ret == -ENOENT || ret == -ENOTSUPP)
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return 0;
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dev_warn(dev, "Can't get reset: %d\n", ret);
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return ret;
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}
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ret = reset_deassert_bulk(&priv->resets);
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if (ret) {
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reset_release_bulk(&priv->resets);
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dev_err(dev, "Failed to reset: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int gpio_dwapb_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *priv = dev_get_uclass_priv(dev);
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struct gpio_dwapb_platdata *plat = dev->platdata;
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if (!plat) {
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/* Reset on parent device only */
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return gpio_dwapb_reset(dev);
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}
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priv->gpio_count = plat->pins;
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priv->bank_name = plat->name;
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return 0;
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}
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static int gpio_dwapb_bind(struct udevice *dev)
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{
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struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
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const void *blob = gd->fdt_blob;
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struct udevice *subdev;
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fdt_addr_t base;
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int ret, node, bank = 0;
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/* If this is a child device, there is nothing to do here */
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if (plat)
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return 0;
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base = dev_read_addr(dev);
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if (base == FDT_ADDR_T_NONE) {
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debug("Can't get the GPIO register base address\n");
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return -ENXIO;
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}
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for (node = fdt_first_subnode(blob, dev_of_offset(dev));
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node > 0;
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node = fdt_next_subnode(blob, node)) {
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if (!fdtdec_get_bool(blob, node, "gpio-controller"))
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continue;
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plat = devm_kcalloc(dev, 1, sizeof(*plat), GFP_KERNEL);
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if (!plat)
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return -ENOMEM;
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plat->base = base;
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plat->bank = bank;
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plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0);
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plat->name = fdt_stringlist_get(blob, node, "bank-name", 0,
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NULL);
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if (!plat->name) {
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/*
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* Fall back to node name. This means accessing pins
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* via bank name won't work.
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*/
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plat->name = fdt_get_name(blob, node, NULL);
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}
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ret = device_bind(dev, dev->driver, plat->name,
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plat, -1, &subdev);
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if (ret)
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return ret;
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dev_set_of_offset(subdev, node);
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bank++;
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}
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return 0;
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}
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static int gpio_dwapb_remove(struct udevice *dev)
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{
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struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
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struct gpio_dwapb_priv *priv = dev_get_priv(dev);
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if (!plat && priv)
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return reset_release_bulk(&priv->resets);
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return 0;
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}
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static const struct udevice_id gpio_dwapb_ids[] = {
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{ .compatible = "snps,dw-apb-gpio" },
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{ }
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};
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U_BOOT_DRIVER(gpio_dwapb) = {
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.name = "gpio-dwapb",
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.id = UCLASS_GPIO,
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.of_match = gpio_dwapb_ids,
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.ops = &gpio_dwapb_ops,
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.bind = gpio_dwapb_bind,
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.probe = gpio_dwapb_probe,
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.remove = gpio_dwapb_remove,
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.priv_auto_alloc_size = sizeof(struct gpio_dwapb_priv),
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};
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