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https://github.com/brain-hackers/u-boot-brain
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![Stefan Roese](/assets/img/avatar_default.png)
This solves some RX problems that have been seen, when using the mvneta ethernet driver. The cache needs to be reset into a "clean" state before using it. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
250 lines
5.7 KiB
C
250 lines
5.7 KiB
C
/*
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* Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
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#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
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static struct mbus_win windows[] = {
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/* PCIE MEM address space */
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{ DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
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/* PCIE IO address space */
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{ DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
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/* SPI */
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{ DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
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CPU_ATTR_SPIFLASH },
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/* NOR */
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{ DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
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CPU_ATTR_BOOTROM },
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};
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void reset_cpu(unsigned long ignored)
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{
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struct mvebu_system_registers *reg =
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(struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
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writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
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writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
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while (1)
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;
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}
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int mvebu_soc_family(void)
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{
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u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
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if (devid == SOC_MV78460_ID)
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return MVEBU_SOC_AXP;
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if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
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devid == SOC_88F6828_ID)
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return MVEBU_SOC_A38X;
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return MVEBU_SOC_UNKNOWN;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
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u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
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puts("SoC: ");
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switch (devid) {
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case SOC_MV78460_ID:
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puts("MV78460-");
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break;
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case SOC_88F6810_ID:
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puts("MV88F6810-");
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break;
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case SOC_88F6820_ID:
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puts("MV88F6820-");
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break;
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case SOC_88F6828_ID:
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puts("MV88F6828-");
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break;
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default:
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puts("Unknown-");
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break;
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}
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if (mvebu_soc_family() == MVEBU_SOC_AXP) {
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switch (revid) {
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case 1:
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puts("A0\n");
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break;
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case 2:
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puts("B0\n");
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break;
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default:
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printf("?? (%x)\n", revid);
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break;
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}
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}
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if (mvebu_soc_family() == MVEBU_SOC_A38X) {
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switch (revid) {
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case MV_88F68XX_Z1_ID:
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puts("Z1\n");
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break;
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case MV_88F68XX_A0_ID:
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puts("A0\n");
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break;
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default:
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printf("?? (%x)\n", revid);
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break;
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}
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}
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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/*
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* This function initialize Controller DRAM Fastpath windows.
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* It takes the CS size information from the 0x1500 scratch registers
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* and sets the correct windows sizes and base addresses accordingly.
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*
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* These values are set in the scratch registers by the Marvell
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* DDR3 training code, which is executed by the BootROM before the
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* main payload (U-Boot) is executed. This training code is currently
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* only available in the Marvell U-Boot version. It needs to be
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* ported to mainline U-Boot SPL at some point.
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*/
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static void update_sdram_window_sizes(void)
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{
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u64 base = 0;
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u32 size, temp;
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int i;
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for (i = 0; i < SDRAM_MAX_CS; i++) {
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size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
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if (size != 0) {
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size |= ~(SDRAM_ADDR_MASK);
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/* Set Base Address */
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temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
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writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
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/*
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* Check if out of max window size and resize
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* the window
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*/
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temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
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~(SDRAM_ADDR_MASK)) | 1;
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temp |= (size & SDRAM_ADDR_MASK);
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writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
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base += ((u64)size + 1);
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} else {
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/*
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* Disable window if not used, otherwise this
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* leads to overlapping enabled windows with
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* pretty strange results
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*/
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clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
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}
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}
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}
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#ifdef CONFIG_ARCH_CPU_INIT
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int arch_cpu_init(void)
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{
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/* Linux expects the internal registers to be at 0xf1000000 */
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writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
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/*
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* We need to call mvebu_mbus_probe() before calling
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* update_sdram_window_sizes() as it disables all previously
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* configured mbus windows and then configures them as
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* required for U-Boot. Calling update_sdram_window_sizes()
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* without this configuration will not work, as the internal
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* registers can't be accessed reliably because of potenial
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* double mapping.
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* After updating the SDRAM access windows we need to call
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* mvebu_mbus_probe() again, as this now correctly configures
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* the SDRAM areas that are later used by the MVEBU drivers
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* (e.g. USB, NETA).
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*/
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/*
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* First disable all windows
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*/
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mvebu_mbus_probe(NULL, 0);
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if (mvebu_soc_family() == MVEBU_SOC_AXP) {
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/*
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* Now the SDRAM access windows can be reconfigured using
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* the information in the SDRAM scratch pad registers
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*/
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update_sdram_window_sizes();
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}
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/*
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* Finally the mbus windows can be configured with the
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* updated SDRAM sizes
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*/
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mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
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return 0;
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}
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#endif /* CONFIG_ARCH_CPU_INIT */
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/*
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* SOC specific misc init
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*/
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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/* Nothing yet, perhaps we need something here later */
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return 0;
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}
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#endif /* CONFIG_ARCH_MISC_INIT */
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#ifdef CONFIG_MVNETA
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int cpu_eth_init(bd_t *bis)
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{
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u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
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MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
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u8 phy_addr[] = CONFIG_PHY_ADDR;
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int i;
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/*
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* Only Armada XP supports all 4 ethernet interfaces. A38x has
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* slightly different base addresses for its 2-3 interfaces.
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*/
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if (mvebu_soc_family() != MVEBU_SOC_AXP) {
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enet_base[1] = MVEBU_EGIGA2_BASE;
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enet_base[2] = MVEBU_EGIGA3_BASE;
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}
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for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
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mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
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return 0;
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}
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Avoid problem with e.g. neta ethernet driver */
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invalidate_dcache_all();
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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