mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 13:46:17 +09:00
2b6051541b
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>
24 lines
579 B
Plaintext
24 lines
579 B
Plaintext
Intel LPC Device Binding
|
|
========================
|
|
|
|
The device tree node which describes the operation of the Intel Low Pin
|
|
Count device is as follows:
|
|
|
|
Required properties :
|
|
- compatible = "intel,lpc"
|
|
- gen-dec : Specifies the values for the gen-dec registers. Up to four cell
|
|
pairs can be provided - the first of each pair is the base address and
|
|
the second is the size. These are written into the GENx_DEC registers of
|
|
the LPC device
|
|
|
|
|
|
Example
|
|
-------
|
|
|
|
lpc {
|
|
compatible = "intel,lpc";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
gen-dec = <0x800 0xfc 0x900 0xfc>;
|
|
};
|