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synced 2024-08-22 09:58:52 +09:00
![Chris Packham](/assets/img/avatar_default.png)
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE. Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
236 lines
7.8 KiB
C
236 lines
7.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _MV_DDR_PLAT_H
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#define _MV_DDR_PLAT_H
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#define MAX_INTERFACE_NUM 1
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#define MAX_BUS_NUM 5
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#define DDR_IF_CTRL_SUBPHYS_NUM 3
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#define DFS_LOW_FREQ_VALUE 120
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#define SDRAM_CS_SIZE 0xfffffff /* FIXME: implement a function for cs size for each platform */
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#define INTER_REGS_BASE SOC_REGS_PHY_BASE
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#define AP_INT_REG_START_ADDR 0xd0000000
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#define AP_INT_REG_END_ADDR 0xd0100000
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/* Controler bus divider 1 for 32 bit, 2 for 64 bit */
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#define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER 1
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/* Tune internal training params values */
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#define TUNE_TRAINING_PARAMS_CK_DELAY 160
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#define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xA
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#define TUNE_TRAINING_PARAMS_PRI_DATA 123
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#define TUNE_TRAINING_PARAMS_NRI_DATA 123
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#define TUNE_TRAINING_PARAMS_PRI_CTRL 74
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#define TUNE_TRAINING_PARAMS_NRI_CTRL 74
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#define TUNE_TRAINING_PARAMS_P_ODT_DATA 45
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#define TUNE_TRAINING_PARAMS_N_ODT_DATA 45
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#define TUNE_TRAINING_PARAMS_P_ODT_CTRL 45
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#define TUNE_TRAINING_PARAMS_N_ODT_CTRL 45
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#define TUNE_TRAINING_PARAMS_DIC 0x2
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#define TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS 0x120012
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#define TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS 0x10000
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#define TUNE_TRAINING_PARAMS_RTT_NOM 0x44
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#define TUNE_TRAINING_PARAMS_RTT_WR_1CS 0x0 /*off*/
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#define TUNE_TRAINING_PARAMS_RTT_WR_2CS 0x0 /*off*/
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#define MARVELL_BOARD MARVELL_BOARD_ID_BASE
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#define REG_DEVICE_SAR1_ADDR 0xe4204
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#define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17
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#define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f
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#define DEVICE_SAMPLE_AT_RESET2_REG 0x18604
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#define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET 0
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#define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ 0
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#define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_40MHZ 1
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/* DRAM Windows */
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#define REG_XBAR_WIN_5_CTRL_ADDR 0x20050
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#define REG_XBAR_WIN_5_BASE_ADDR 0x20054
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/* DRAM Windows */
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#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
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#define REG_XBAR_WIN_4_BASE_ADDR 0x20044
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#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
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#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
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#define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0
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#define REG_XBAR_WIN_16_BASE_ADDR 0x200d4
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#define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc
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#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
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#define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win))
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#define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win))
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#define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100))
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#define CPU_MRVL_ID_OFFSET 0x10
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#define SAR1_CPU_CORE_MASK 0x00000018
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#define SAR1_CPU_CORE_OFFSET 3
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/* SatR defined too change topology busWidth and ECC configuration */
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#define DDR_SATR_CONFIG_MASK_WIDTH 0x8
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#define DDR_SATR_CONFIG_MASK_ECC 0x10
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#define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20
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#define REG_SAMPLE_RESET_HIGH_ADDR 0x18600
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#define MV_BOARD_REFCLK_25MHZ 25000000
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#define MV_BOARD_REFCLK MV_BOARD_REFCLK_25MHZ
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#define MAX_DQ_NUM 40
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/* dram line buffer registers */
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#define DLB_CTRL_REG 0x1700
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#define DLB_EN_OFFS 0
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#define DLB_EN_MASK 0x1
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#define DLB_EN_ENA 1
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#define DLB_EN_DIS 0
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#define WR_COALESCE_EN_OFFS 2
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#define WR_COALESCE_EN_MASK 0x1
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#define WR_COALESCE_EN_ENA 1
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#define WR_COALESCE_EN_DIS 0
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#define AXI_PREFETCH_EN_OFFS 3
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#define AXI_PREFETCH_EN_MASK 0x1
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#define AXI_PREFETCH_EN_ENA 1
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#define AXI_PREFETCH_EN_DIS 0
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#define MBUS_PREFETCH_EN_OFFS 4
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#define MBUS_PREFETCH_EN_MASK 0x1
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#define MBUS_PREFETCH_EN_ENA 1
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#define MBUS_PREFETCH_EN_DIS 0
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#define PREFETCH_NXT_LN_SZ_TRIG_OFFS 6
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#define PREFETCH_NXT_LN_SZ_TRIG_MASK 0x1
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#define PREFETCH_NXT_LN_SZ_TRIG_ENA 1
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#define PREFETCH_NXT_LN_SZ_TRIG_DIS 0
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#define DLB_BUS_OPT_WT_REG 0x1704
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#define DLB_AGING_REG 0x1708
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#define DLB_EVICTION_CTRL_REG 0x170c
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#define DLB_EVICTION_TIMERS_REG 0x1710
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#define DLB_USER_CMD_REG 0x1714
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#define DLB_WTS_DIFF_CS_REG 0x1770
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#define DLB_WTS_DIFF_BG_REG 0x1774
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#define DLB_WTS_SAME_BG_REG 0x1778
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#define DLB_WTS_CMDS_REG 0x177c
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#define DLB_WTS_ATTR_PRIO_REG 0x1780
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#define DLB_QUEUE_MAP_REG 0x1784
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#define DLB_SPLIT_REG 0x1788
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/* Subphy result control per byte registers */
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#define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830
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#define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834
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#define RESULT_CONTROL_BYTE_PUP_2_REG 0x1838
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#define RESULT_CONTROL_BYTE_PUP_3_REG 0x183c
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#define RESULT_CONTROL_BYTE_PUP_4_REG 0x18b0
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/* Subphy result control per bit registers */
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#define RESULT_CONTROL_PUP_0_BIT_0_REG 0x18b4
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#define RESULT_CONTROL_PUP_0_BIT_1_REG 0x18b8
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#define RESULT_CONTROL_PUP_0_BIT_2_REG 0x18bc
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#define RESULT_CONTROL_PUP_0_BIT_3_REG 0x18c0
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#define RESULT_CONTROL_PUP_0_BIT_4_REG 0x18c4
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#define RESULT_CONTROL_PUP_0_BIT_5_REG 0x18c8
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#define RESULT_CONTROL_PUP_0_BIT_6_REG 0x18cc
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#define RESULT_CONTROL_PUP_0_BIT_7_REG 0x18f0
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#define RESULT_CONTROL_PUP_1_BIT_0_REG 0x18f4
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#define RESULT_CONTROL_PUP_1_BIT_1_REG 0x18f8
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#define RESULT_CONTROL_PUP_1_BIT_2_REG 0x18fc
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#define RESULT_CONTROL_PUP_1_BIT_3_REG 0x1930
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#define RESULT_CONTROL_PUP_1_BIT_4_REG 0x1934
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#define RESULT_CONTROL_PUP_1_BIT_5_REG 0x1938
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#define RESULT_CONTROL_PUP_1_BIT_6_REG 0x193c
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#define RESULT_CONTROL_PUP_1_BIT_7_REG 0x19b0
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#define RESULT_CONTROL_PUP_2_BIT_0_REG 0x19b4
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#define RESULT_CONTROL_PUP_2_BIT_1_REG 0x19b8
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#define RESULT_CONTROL_PUP_2_BIT_2_REG 0x19bc
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#define RESULT_CONTROL_PUP_2_BIT_3_REG 0x19c0
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#define RESULT_CONTROL_PUP_2_BIT_4_REG 0x19c4
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#define RESULT_CONTROL_PUP_2_BIT_5_REG 0x19c8
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#define RESULT_CONTROL_PUP_2_BIT_6_REG 0x19cc
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#define RESULT_CONTROL_PUP_2_BIT_7_REG 0x19f0
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#define RESULT_CONTROL_PUP_3_BIT_0_REG 0x19f4
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#define RESULT_CONTROL_PUP_3_BIT_1_REG 0x19f8
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#define RESULT_CONTROL_PUP_3_BIT_2_REG 0x19fc
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#define RESULT_CONTROL_PUP_3_BIT_3_REG 0x1a30
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#define RESULT_CONTROL_PUP_3_BIT_4_REG 0x1a34
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#define RESULT_CONTROL_PUP_3_BIT_5_REG 0x1a38
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#define RESULT_CONTROL_PUP_3_BIT_6_REG 0x1a3c
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#define RESULT_CONTROL_PUP_3_BIT_7_REG 0x1ab0
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#define RESULT_CONTROL_PUP_4_BIT_0_REG 0x1ab4
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#define RESULT_CONTROL_PUP_4_BIT_1_REG 0x1ab8
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#define RESULT_CONTROL_PUP_4_BIT_2_REG 0x1abc
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#define RESULT_CONTROL_PUP_4_BIT_3_REG 0x1ac0
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#define RESULT_CONTROL_PUP_4_BIT_4_REG 0x1ac4
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#define RESULT_CONTROL_PUP_4_BIT_5_REG 0x1ac8
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#define RESULT_CONTROL_PUP_4_BIT_6_REG 0x1acc
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#define RESULT_CONTROL_PUP_4_BIT_7_REG 0x1af0
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/* CPU */
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#define REG_BOOTROM_ROUTINE_ADDR 0x182d0
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#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12
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/* Matrix enables DRAM modes (bus width/ECC) per boardId */
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#define TOPOLOGY_UPDATE_32BIT 0
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#define TOPOLOGY_UPDATE_32BIT_ECC 1
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#define TOPOLOGY_UPDATE_16BIT 2
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#define TOPOLOGY_UPDATE_16BIT_ECC 3
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#define TOPOLOGY_UPDATE_16BIT_ECC_PUP3 4
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#define TOPOLOGY_UPDATE { \
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/* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \
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{1, 1, 1, 1, 1}, /* RD_NAS_68XX_ID */ \
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{1, 1, 1, 1, 1}, /* DB_68XX_ID */ \
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{1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \
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{1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \
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{1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \
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{0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \
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{1, 1, 1, 1, 1} /* DB_AMC_6820_ID */ \
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};
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enum {
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CPU_1066MHZ_DDR_400MHZ,
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CPU_RESERVED_DDR_RESERVED0,
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CPU_667MHZ_DDR_667MHZ,
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CPU_800MHZ_DDR_800MHZ,
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CPU_RESERVED_DDR_RESERVED1,
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CPU_RESERVED_DDR_RESERVED2,
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CPU_RESERVED_DDR_RESERVED3,
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LAST_FREQ
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};
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/* struct used for DLB configuration array */
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struct dlb_config {
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u32 reg_addr;
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u32 reg_data;
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};
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#define ACTIVE_INTERFACE_MASK 0x1
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extern u32 dmin_phy_reg_table[][2];
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extern u16 odt_slope[];
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extern u16 odt_intercept[];
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int mv_ddr_pre_training_soc_config(const char *ddr_type);
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int mv_ddr_post_training_soc_config(const char *ddr_type);
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void mv_ddr_mem_scrubbing(void);
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void mv_ddr_odpg_enable(void);
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void mv_ddr_odpg_disable(void);
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void mv_ddr_odpg_done_clr(void);
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int mv_ddr_is_odpg_done(u32 count);
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void mv_ddr_training_enable(void);
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int mv_ddr_is_training_done(u32 count, u32 *result);
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u32 mv_ddr_dm_pad_get(void);
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int mv_ddr_pre_training_fixup(void);
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int mv_ddr_post_training_fixup(void);
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int mv_ddr_manual_cal_do(void);
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#endif /* _MV_DDR_PLAT_H */
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