Ley Foon Tan 2b09ea48dd arm: socfpga: Restructure reset manager driver ... Restructure reset manager driver in the preparation to support A10. Move the Gen5 specific code to gen5 files. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>		2017-05-18 11:33:17 +02:00
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base_addr_a10.h	ARM: socfpga: arria10: add base address map for Arria10	2015-11-30 13:30:19 +01:00
base_addr_ac5.h	ARM: socfpga: rename the cyclone5 and arria5 base address file	2015-11-30 13:30:19 +01:00
boot0.h	ARM: socfpga: boot0 hook: remove macro from boot0 header file	2017-04-14 14:06:42 +02:00
clock_manager_gen5.h	arm: socfpga: Restructure clock manager driver	2017-05-18 11:33:16 +02:00
clock_manager.h	arm: socfpga: Restructure clock manager driver	2017-05-18 11:33:16 +02:00
fpga_manager.h	ARM: socfpga: move SoC headers to mach-socfpga/include/mach	2015-05-07 05:21:15 +02:00
freeze_controller.h	ARM: socfpga: move SoC headers to mach-socfpga/include/mach	2015-05-07 05:21:15 +02:00
gpio.h	ARM: socfpga: move SoC headers to mach-socfpga/include/mach	2015-05-07 05:21:15 +02:00
nic301.h	ARM: socfpga: move SoC headers to mach-socfpga/include/mach	2015-05-07 05:21:15 +02:00
reset_manager_gen5.h	arm: socfpga: Restructure reset manager driver	2017-05-18 11:33:17 +02:00
reset_manager.h	arm: socfpga: Restructure reset manager driver	2017-05-18 11:33:17 +02:00
scan_manager.h	arm: socfpga: scan: Add code to get FPGA ID	2015-08-08 14:14:30 +02:00
scu.h	ARM: socfpga: move SoC headers to mach-socfpga/include/mach	2015-05-07 05:21:15 +02:00
sdram.h	ddr: altera: Configuring SDRAM extra cycles timing parameters	2016-10-27 08:03:07 +02:00
system_manager.h	arm: socfpga: fix up a questionable macro for SDMMC	2015-12-20 03:44:56 +01:00
timer.h	ARM: socfpga: move SoC headers to mach-socfpga/include/mach	2015-05-07 05:21:15 +02:00