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https://github.com/brain-hackers/u-boot-brain
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![Stefan Roese](/assets/img/avatar_default.png)
The SPL implementation for SPEAr600 is older than the common SPL infrastructure. This patch now moves the SPEAr600 SPL over to the common SPL code. Tested on the only SPEAr board that currently uses SPL in mainline U-Boot, the x600. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com>
258 lines
5.7 KiB
C
258 lines
5.7 KiB
C
/*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Copyright (C) 2012 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <version.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_defs.h>
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#include <asm/arch/spr_misc.h>
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#include <asm/arch/spr_syscntl.h>
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#include <linux/mtd/st_smi.h>
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static void ddr_clock_init(void)
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{
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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u32 clkenb, ddrpll;
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clkenb = readl(&misc_p->periph1_clken);
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clkenb &= ~PERIPH_MPMCMSK;
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clkenb |= PERIPH_MPMC_WE;
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/* Intentionally done twice */
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writel(clkenb, &misc_p->periph1_clken);
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writel(clkenb, &misc_p->periph1_clken);
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ddrpll = readl(&misc_p->pll_ctr_reg);
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ddrpll &= ~MEM_CLK_SEL_MSK;
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#if (CONFIG_DDR_HCLK)
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ddrpll |= MEM_CLK_HCLK;
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#elif (CONFIG_DDR_2HCLK)
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ddrpll |= MEM_CLK_2HCLK;
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#elif (CONFIG_DDR_PLL2)
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ddrpll |= MEM_CLK_PLL2;
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#else
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#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
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#endif
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writel(ddrpll, &misc_p->pll_ctr_reg);
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writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
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&misc_p->periph1_clken);
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}
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static void mpmc_init_values(void)
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{
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u32 i;
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u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
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u32 *mpmc_val_p = &mpmc_conf_vals[0];
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for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
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writel(*mpmc_val_p, mpmc_reg_p);
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mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
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/*
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* MPMC controller start
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* MPMC waiting for DLLLOCKREG high
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*/
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writel(0x01000100, &mpmc_reg_p[7]);
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while (!(readl(&mpmc_reg_p[3]) & 0x10000))
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;
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}
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static void mpmc_init(void)
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{
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/* Clock related settings for DDR */
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ddr_clock_init();
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/*
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* DDR pad register bits are different for different SoCs
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* Compensation values are also handled separately
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*/
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plat_ddr_init();
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/* Initialize mpmc register values */
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mpmc_init_values();
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}
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static void pll_init(void)
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{
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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/* Initialize PLLs */
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writel(FREQ_332, &misc_p->pll1_frq);
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writel(0x1C0A, &misc_p->pll1_cntl);
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writel(0x1C0E, &misc_p->pll1_cntl);
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writel(0x1C06, &misc_p->pll1_cntl);
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writel(0x1C0E, &misc_p->pll1_cntl);
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writel(FREQ_332, &misc_p->pll2_frq);
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writel(0x1C0A, &misc_p->pll2_cntl);
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writel(0x1C0E, &misc_p->pll2_cntl);
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writel(0x1C06, &misc_p->pll2_cntl);
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writel(0x1C0E, &misc_p->pll2_cntl);
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/* wait for pll locks */
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while (!(readl(&misc_p->pll1_cntl) & 0x1))
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;
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while (!(readl(&misc_p->pll2_cntl) & 0x1))
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;
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}
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static void mac_init(void)
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{
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
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&misc_p->periph1_clken);
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writel(SYNTH23, &misc_p->gmac_synth_clk);
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switch (get_socrev()) {
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case SOC_SPEAR600_AA:
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case SOC_SPEAR600_AB:
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case SOC_SPEAR600_BA:
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case SOC_SPEAR600_BB:
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case SOC_SPEAR600_BC:
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case SOC_SPEAR600_BD:
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writel(0x0, &misc_p->gmac_ctr_reg);
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break;
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case SOC_SPEAR300:
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case SOC_SPEAR310:
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case SOC_SPEAR320:
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writel(0x4, &misc_p->gmac_ctr_reg);
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break;
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}
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writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
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&misc_p->periph1_clken);
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writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
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&misc_p->periph1_rst);
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writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
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&misc_p->periph1_rst);
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}
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static void sys_init(void)
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{
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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struct syscntl_regs *syscntl_p =
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(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
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/* Set system state to SLOW */
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writel(SLOW, &syscntl_p->scctrl);
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writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
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/* Initialize PLLs */
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pll_init();
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/*
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* Ethernet configuration
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* To be done only if the tftp boot is not selected already
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* Boot code ensures the correct configuration in tftp booting
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*/
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if (!tftp_boot_selected())
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mac_init();
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writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
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writel(0x555, &misc_p->amba_clk_cfg);
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writel(NORMAL, &syscntl_p->scctrl);
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/* Wait for system to switch to normal mode */
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while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
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!= NORMAL)
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;
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}
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/*
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* get_socrev
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*
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* Get SoC Revision.
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* @return SOC_SPEARXXX
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*/
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int get_socrev(void)
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{
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#if defined(CONFIG_SPEAR600)
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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u32 soc_id = readl(&misc_p->soc_core_id);
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u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
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u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
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if ((pri_socid == 'B') && (sec_socid == 'B'))
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return SOC_SPEAR600_BB;
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else if ((pri_socid == 'B') && (sec_socid == 'C'))
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return SOC_SPEAR600_BC;
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else if ((pri_socid == 'B') && (sec_socid == 'D'))
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return SOC_SPEAR600_BD;
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else if (soc_id == 0)
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return SOC_SPEAR600_BA;
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else
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return SOC_SPEAR_NA;
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#elif defined(CONFIG_SPEAR300)
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return SOC_SPEAR300;
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#elif defined(CONFIG_SPEAR310)
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return SOC_SPEAR310;
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#elif defined(CONFIG_SPEAR320)
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return SOC_SPEAR320;
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#endif
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}
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/*
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* SNOR (Serial NOR flash) related functions
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*/
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static void snor_init(void)
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{
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struct smi_regs *const smicntl =
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(struct smi_regs * const)CONFIG_SYS_SMI_BASE;
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/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
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writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
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&smicntl->smi_cr1);
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}
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u32 spl_boot_device(void)
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{
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u32 mode;
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/* Currently only SNOR is supported as the only */
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if (snor_boot_selected()) {
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/* SNOR-SMI initialization */
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snor_init();
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mode = BOOT_DEVICE_NOR;
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}
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return mode;
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}
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void board_init_f(ulong dummy)
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{
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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/* Initialize PLLs */
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sys_init();
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preloader_console_init();
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arch_cpu_init();
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/* Enable IPs (release reset) */
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writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
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/* Initialize MPMC */
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puts("Configure DDR\n");
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mpmc_init();
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spear_late_init();
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board_init_r(NULL, 0);
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}
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