mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
ffdf9f9ae0
This is based on Thierry Reding's work and uses Ian Campell's preparatory patches. It comes with full support for CPU_ON/OFF PSCI services. The algorithm used in this version for turning CPUs on and off was proposed by Peter De Schrijver and Thierry Reding in http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It consists of first enabling CPU1..3 via the PMC, just to powergate them again with the help of the Flow Controller. Once the Flow Controller is in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF PSCI requests. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/*
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* (C) Copyright 2015, Siemens AG
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* Author: Jan Kiszka <jan.kiszka@siemens.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/psci.h>
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#include <asm/arch/flow.h>
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#include <asm/arch/powergate.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/pmc.h>
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static void park_cpu(void)
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{
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while (1)
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asm volatile("wfi");
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}
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/**
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* Initialize power management for application processors
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*/
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void psci_board_init(void)
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{
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
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writel((u32)park_cpu, EXCEP_VECTOR_CPU_RESET_VECTOR);
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/*
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* The naturally expected order of putting these CPUs under Flow
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* Controller regime would be
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* - configure the Flow Controller
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* - power up the CPUs
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* - wait for the CPUs to hit wfi and be powered down again
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*
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* However, this doesn't work in practice. We rather need to power them
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* up first and park them in wfi. While they are waiting there, we can
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* indeed program the Flow Controller to powergate them on wfi, which
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* will then happen immediately as they are already in that state.
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*/
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tegra_powergate_power_on(TEGRA_POWERGATE_CPU1);
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tegra_powergate_power_on(TEGRA_POWERGATE_CPU2);
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tegra_powergate_power_on(TEGRA_POWERGATE_CPU3);
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writel((2 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu1_csr);
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writel((4 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu2_csr);
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writel((8 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu3_csr);
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writel(EVENT_MODE_STOP, &flow->halt_cpu1_events);
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writel(EVENT_MODE_STOP, &flow->halt_cpu2_events);
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writel(EVENT_MODE_STOP, &flow->halt_cpu3_events);
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while (!(readl(&flow->cpu1_csr) & CSR_PWR_OFF_STS) ||
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!(readl(&flow->cpu2_csr) & CSR_PWR_OFF_STS) ||
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!(readl(&flow->cpu3_csr) & CSR_PWR_OFF_STS))
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/* wait */;
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}
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