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https://github.com/brain-hackers/u-boot-brain
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e6e505b93c
Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while most of it is just generic code that could as well be used on an AArch64 SoC. Move all files that are not really tied to armv7 into a new mach-sunxi directory. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
118 lines
2.9 KiB
C
118 lines
2.9 KiB
C
/*
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* Sunxi A31 Power Management Unit
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*
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* (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
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* http://linux-sunxi.org
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*
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* Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
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*
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* (C) Copyright 2006-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Berg Xing <bergxing@allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/p2wi.h>
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#include <asm/arch/prcm.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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void p2wi_init(void)
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{
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struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
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/* Enable p2wi and PIO clk, and de-assert their resets */
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prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
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sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
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sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
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/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
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writel(P2WI_CTRL_RESET, &p2wi->ctrl);
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sdelay(0x100);
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writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
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&p2wi->cc);
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}
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int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
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{
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struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
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unsigned long tmo = timer_get_us() + 1000000;
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writel(P2WI_PM_DEV_ADDR(slave_addr) |
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P2WI_PM_CTRL_ADDR(ctrl_reg) |
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P2WI_PM_INIT_DATA(init_data) |
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P2WI_PM_INIT_SEND,
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&p2wi->pm);
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while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
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if (timer_get_us() > tmo)
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return -ETIME;
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}
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return 0;
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}
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static int p2wi_await_trans(void)
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{
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struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
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unsigned long tmo = timer_get_us() + 1000000;
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int ret;
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u8 reg;
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while (1) {
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reg = readl(&p2wi->status);
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if (reg & P2WI_STAT_TRANS_ERR) {
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ret = -EIO;
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break;
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}
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if (reg & P2WI_STAT_TRANS_DONE) {
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ret = 0;
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break;
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}
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if (timer_get_us() > tmo) {
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ret = -ETIME;
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break;
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}
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}
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writel(reg, &p2wi->status); /* Clear status bits */
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return ret;
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}
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int p2wi_read(const u8 addr, u8 *data)
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{
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struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
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int ret;
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writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
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writel(P2WI_DATA_NUM_BYTES(1) |
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P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
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writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
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writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
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ret = p2wi_await_trans();
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*data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
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return ret;
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}
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int p2wi_write(const u8 addr, u8 data)
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{
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struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
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writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
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writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
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writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
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writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
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writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
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return p2wi_await_trans();
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}
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