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https://github.com/brain-hackers/u-boot-brain
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b24f119d67
Hello,
Attached is a patch implementing multiple I2C buses on the MPC834x CPU
family and the MPC8349EMDS board in particular.
This patch requires Patch 1 (Add support for multiple I2C buses).
Testing was performed on a 533MHz board.
/*** Note: This patch replaces ticket DNX#2006083042000027 ***/
Signed-off-by: Ben Warren <bwarren@qstreams.com>
CHANGELOG:
Implemented driver-level code to support two I2C buses on the
MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds
are 50kHz, 100kHz and 400kHz on each bus.
regards,
Ben
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
/*
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* Freescale I2C Controller
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2003, Motorola, Inc.
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* author: Eran Liberty (liberty@freescale.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_I2C_H_
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#define _ASM_I2C_H_
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#include <asm/types.h>
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typedef struct i2c
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{
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u8 adr; /**< I2C slave address */
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#define I2C_ADR 0xFE
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#define I2C_ADR_SHIFT 1
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#define I2C_ADR_RES ~(I2C_ADR)
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u8 res0[3];
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u8 fdr; /**< I2C frequency divider register */
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#define IC2_FDR 0x3F
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#define IC2_FDR_SHIFT 0
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#define IC2_FDR_RES ~(IC2_FDR)
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u8 res1[3];
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u8 cr; /**< I2C control redister */
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#define I2C_CR_MEN 0x80
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#define I2C_CR_MIEN 0x40
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#define I2C_CR_MSTA 0x20
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#define I2C_CR_MTX 0x10
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#define I2C_CR_TXAK 0x08
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#define I2C_CR_RSTA 0x04
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#define I2C_CR_BCST 0x01
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u8 res2[3];
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u8 sr; /**< I2C status register */
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#define I2C_SR_MCF 0x80
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#define I2C_SR_MAAS 0x40
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#define I2C_SR_MBB 0x20
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#define I2C_SR_MAL 0x10
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#define I2C_SR_BCSTM 0x08
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#define I2C_SR_SRW 0x04
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#define I2C_SR_MIF 0x02
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#define I2C_SR_RXAK 0x01
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u8 res3[3];
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u8 dr; /**< I2C data register */
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#define I2C_DR 0xFF
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#define I2C_DR_SHIFT 0
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#define I2C_DR_RES ~(I2C_DR)
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u8 res4[3];
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u8 dfsrr; /**< I2C digital filter sampling rate register */
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#define I2C_DFSRR 0x3F
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#define I2C_DFSRR_SHIFT 0
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#define I2C_DFSRR_RES ~(I2C_DR)
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u8 res5[3];
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u8 res6[0xE8];
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} i2c_t;
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#ifndef CFG_HZ
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#error CFG_HZ is not defined in /include/configs/${BOARD}.h
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#endif
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#define I2C_TIMEOUT (CFG_HZ/4)
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enum I2C_BUS_NUM
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{
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I2C_BUS_1 = 0,
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I2C_BUS_2,
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};
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#ifndef CFG_IMMRBAR
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#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h
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#endif
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#ifndef CFG_I2C_OFFSET
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#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
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#endif
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#define I2C_1 ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET))
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/* Optional support for second I2C bus */
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#ifdef CFG_I2C2_OFFSET
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#define I2C_2 ((i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET))
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#endif /* CFG_I2C2_OFFSET */
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#define I2C_READ 1
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#define I2C_WRITE 0
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#endif /* _ASM_I2C_H_ */
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