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![Stefan Roese](/assets/img/avatar_default.png)
- Support for TQM8541/8555 boards added. - Complete rework of TQM8540/8560 support. - Common TQM85xx code now supports all current TQM85xx platforms (TQM8540/8541/8555/8560). - DDR SDRAM size detection added. - CAS latency default values can be overwritten by setting "serial#" to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used. If problems are detected with this non default CAS latency, the defualt values will be used instead. - FLASH size detection added. - Moved FCC ethernet driver initialization behind TSEC driver init -> TSEC is first device. Patch by Stefan Roese, 30 Nov 2005
227 lines
4.9 KiB
C
227 lines
4.9 KiB
C
/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <spd.h>
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struct sdram_conf_s {
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unsigned long size;
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unsigned long reg;
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};
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typedef struct sdram_conf_s sdram_conf_t;
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sdram_conf_t ddr_cs_conf[] = {
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{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
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{(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
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{(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
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{(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
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};
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#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
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int cas_latency(void);
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/*
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* Autodetect onboard DDR SDRAM on 85xx platforms
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*
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* NOTE: Some of the hardcoded values are hardware dependant,
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* so this should be extended for other future boards
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* using this routine!
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*/
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long int sdram_setup(int casl)
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{
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int i;
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile ccsr_ddr_t *ddr = &immap->im_ddr;
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unsigned long cfg_ddr_timing1;
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unsigned long cfg_ddr_mode;
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/*
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* Disable memory controller.
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*/
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ddr->cs0_config = 0;
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ddr->sdram_cfg = 0;
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switch (casl) {
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case 20:
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cfg_ddr_timing1 = 0x47405331 | (3 << 16);
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cfg_ddr_mode = 0x40020002 | (2 << 4);
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break;
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case 25:
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cfg_ddr_timing1 = 0x47405331 | (4 << 16);
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cfg_ddr_mode = 0x40020002 | (6 << 4);
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break;
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case 30:
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default:
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cfg_ddr_timing1 = 0x47405331 | (5 << 16);
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cfg_ddr_mode = 0x40020002 | (3 << 4);
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break;
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}
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ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
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ddr->cs0_config = ddr_cs_conf[0].reg;
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ddr->timing_cfg_1 = cfg_ddr_timing1;
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ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
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ddr->sdram_mode = cfg_ddr_mode;
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ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
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ddr->err_disable = 0x0000000D;
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asm ("sync;isync;msync");
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udelay(1000);
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ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
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asm ("sync; isync; msync");
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udelay(1000);
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for (i=0; i<N_DDR_CS_CONF; i++) {
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ddr->cs0_config = ddr_cs_conf[i].reg;
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if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) {
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/*
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* OK, size detected -> all done
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*/
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return ddr_cs_conf[i].size;
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}
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}
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return 0; /* nothing found ! */
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}
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void board_add_ram_info(int use_default)
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{
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int casl;
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if (use_default)
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casl = CONFIG_DDR_DEFAULT_CL;
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else
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casl = cas_latency();
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puts(" (CL=");
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switch (casl) {
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case 20:
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puts("2)");
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break;
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case 25:
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puts("2.5)");
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break;
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case 30:
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puts("3)");
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break;
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}
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}
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long int initdram (int board_type)
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{
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long dram_size = 0;
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int casl;
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#if defined(CONFIG_DDR_DLL)
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/*
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* This DLL-Override only used on TQM8540 and TQM8560
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*/
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile ccsr_gur_t *gur= &immap->im_gur;
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int i,x;
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x = 10;
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/*
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* Work around to stabilize DDR DLL
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*/
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gur->ddrdllcr = 0x81000000;
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asm("sync;isync;msync");
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udelay (200);
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while (gur->ddrdllcr != 0x81000100) {
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gur->devdisr = gur->devdisr | 0x00010000;
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asm("sync;isync;msync");
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for (i=0; i<x; i++)
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;
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gur->devdisr = gur->devdisr & 0xfff7ffff;
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asm("sync;isync;msync");
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x++;
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}
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}
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#endif
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casl = cas_latency();
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dram_size = sdram_setup(casl);
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if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
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/*
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* Try again with default CAS latency
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*/
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puts("Problem with CAS lantency");
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board_add_ram_info(1);
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puts(", using default CL!\n");
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casl = CONFIG_DDR_DEFAULT_CL;
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dram_size = sdram_setup(casl);
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puts(" ");
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}
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return dram_size;
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}
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) CFG_MEMTEST_START;
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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printf ("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf ("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf ("SDRAM test passed.\n");
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return 0;
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}
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#endif
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