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https://github.com/brain-hackers/u-boot-brain
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84b124db35
The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
21 lines
424 B
C
21 lines
424 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/test.h>
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static int dm_test_reset(struct unit_test_state *uts)
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{
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struct udevice *dev_cache;
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struct cache_info;
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ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
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ut_assertok(cache_get_info(dev, &info));
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return 0;
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}
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DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT);
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