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https://github.com/brain-hackers/u-boot-brain
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c40b6df87f
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
30 lines
880 B
C
30 lines
880 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Copyright (C) 2018 SiFive, Inc.
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* Wesley Terpstra
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __LINUX_CLK_SIFIVE_FU540_PRCI_H
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#define __LINUX_CLK_SIFIVE_FU540_PRCI_H
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/* Clock indexes for use by Device Tree data */
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#define PRCI_CLK_COREPLL 0
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#define PRCI_CLK_DDRPLL 1
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#define PRCI_CLK_GEMGXLPLL 2
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#define PRCI_CLK_TLCLK 3
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#endif
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