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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
193 lines
5.3 KiB
C
193 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011-2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <asm/processor.h>
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#include "../init.h"
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#include "ddrphy-init.h"
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#include "umc-regs.h"
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#define DRAM_CH_NR 2
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enum dram_freq {
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DRAM_FREQ_1333M,
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DRAM_FREQ_1600M,
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DRAM_FREQ_NR,
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};
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enum dram_size {
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DRAM_SZ_128M,
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DRAM_SZ_256M,
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DRAM_SZ_NR,
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};
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static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17};
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static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24};
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static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
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{0x00240512, 0x00350512},
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{0x002b0617, 0x003f0617},
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};
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static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
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static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};
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static int umc_get_rank(int ch)
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{
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return ch; /* ch0: rank0, ch1: rank1 for this SoC */
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}
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static void umc_start_ssif(void __iomem *ssif_base)
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{
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writel(0x00000000, ssif_base + 0x0000b004);
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writel(0xffffffff, ssif_base + 0x0000c004);
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writel(0x000fffcf, ssif_base + 0x0000c008);
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writel(0x00000001, ssif_base + 0x0000b000);
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writel(0x00000001, ssif_base + 0x0000c000);
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writel(0x03010101, ssif_base + UMC_MDMCHSEL);
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writel(0x03010100, ssif_base + UMC_DMDCHSEL);
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writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
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writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
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writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
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writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
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writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
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writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
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writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
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writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
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writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
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writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
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writel(0x00000001, ssif_base + UMC_CPURST);
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writel(0x00000001, ssif_base + UMC_IDSRST);
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writel(0x00000001, ssif_base + UMC_IXMRST);
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writel(0x00000001, ssif_base + UMC_MDMRST);
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writel(0x00000001, ssif_base + UMC_MDDRST);
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writel(0x00000001, ssif_base + UMC_SIORST);
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writel(0x00000001, ssif_base + UMC_VIORST);
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writel(0x00000001, ssif_base + UMC_FRCRST);
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writel(0x00000001, ssif_base + UMC_RGLRST);
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writel(0x00000001, ssif_base + UMC_AIORST);
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writel(0x00000001, ssif_base + UMC_DMDRST);
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}
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static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
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int freq, unsigned long size, bool ddr3plus)
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{
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enum dram_freq freq_e;
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enum dram_size size_e;
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if (!ddr3plus) {
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pr_err("DDR3 standard is not supported\n");
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return -EINVAL;
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}
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switch (freq) {
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case 1333:
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freq_e = DRAM_FREQ_1333M;
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break;
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case 1600:
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freq_e = DRAM_FREQ_1600M;
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break;
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default:
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pr_err("unsupported DRAM frequency %d MHz\n", freq);
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return -EINVAL;
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}
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switch (size) {
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case 0:
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return 0;
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case SZ_128M:
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size_e = DRAM_SZ_128M;
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break;
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case SZ_256M:
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size_e = DRAM_SZ_256M;
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break;
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default:
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pr_err("unsupported DRAM size 0x%08lx\n", size);
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return -EINVAL;
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}
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writel(umc_cmdctla_plus[freq_e], dc_base + UMC_CMDCTLA);
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writel(umc_cmdctlb_plus[freq_e], dc_base + UMC_CMDCTLB);
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writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
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writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
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writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
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writel(0x04060806, dc_base + UMC_WDATACTL_D0);
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writel(0x04a02000, dc_base + UMC_DATASET);
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writel(0x00000000, ca_base + 0x2300);
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writel(0x00400020, dc_base + UMC_DCCGCTL);
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writel(0x00000003, dc_base + 0x7000);
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writel(0x0000000f, dc_base + 0x8000);
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writel(0x000000c3, dc_base + 0x8004);
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writel(0x00000071, dc_base + 0x8008);
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writel(0x0000003b, dc_base + UMC_DICGCTLA);
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writel(0x020a0808, dc_base + UMC_DICGCTLB);
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writel(0x00000004, dc_base + UMC_FLOWCTLG);
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writel(0x80000201, ca_base + 0xc20);
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writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
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writel(0x00200000, dc_base + UMC_FLOWCTLB);
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writel(0x00004444, dc_base + UMC_FLOWCTLC);
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writel(0x200a0a00, dc_base + UMC_SPCSETB);
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writel(0x00000000, dc_base + UMC_SPCSETD);
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writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
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return 0;
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}
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static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
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int freq, unsigned long size, bool ddr3plus, int ch)
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{
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void __iomem *phy_base = dc_base + 0x00001000;
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int ret;
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writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
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while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
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cpu_relax();
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writel(0x00000101, dc_base + UMC_DIOCTLA);
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ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
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if (ret)
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return ret;
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ddrphy_prepare_training(phy_base, umc_get_rank(ch));
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ret = ddrphy_training(phy_base);
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if (ret)
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return ret;
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return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
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}
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int uniphier_ld4_umc_init(const struct uniphier_board_data *bd)
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{
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void __iomem *umc_base = (void __iomem *)0x5b800000;
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void __iomem *ca_base = umc_base + 0x00001000;
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void __iomem *dc_base = umc_base + 0x00400000;
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void __iomem *ssif_base = umc_base;
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int ch, ret;
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for (ch = 0; ch < DRAM_CH_NR; ch++) {
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ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
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bd->dram_ch[ch].size,
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!!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
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if (ret) {
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pr_err("failed to initialize UMC ch%d\n", ch);
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return ret;
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}
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ca_base += 0x00001000;
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dc_base += 0x00200000;
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}
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umc_start_ssif(ssif_base);
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return 0;
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}
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