mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 09:58:52 +09:00
![Adam Ford](/assets/img/avatar_default.png)
Four different boards had different options for enabling cache that were virtually all the same. This consolidates these common functions into arch/arm/cpu/arm926ejs/cache.c This also has the positive side-effect of enabling cache on the Davinci (da850) boards. Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Add mach-at91 to the list of consolidations] Signed-off-by: Tom Rini <trini@konsulko.com>
91 lines
1.7 KiB
C
91 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2011
|
|
* Ilya Yanok, EmCraft Systems
|
|
*/
|
|
#include <linux/types.h>
|
|
#include <common.h>
|
|
|
|
#ifndef CONFIG_SYS_DCACHE_OFF
|
|
void invalidate_dcache_all(void)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
|
|
}
|
|
|
|
void flush_dcache_all(void)
|
|
{
|
|
asm volatile(
|
|
"0:"
|
|
"mrc p15, 0, r15, c7, c14, 3\n"
|
|
"bne 0b\n"
|
|
"mcr p15, 0, %0, c7, c10, 4\n"
|
|
: : "r"(0) : "memory"
|
|
);
|
|
}
|
|
|
|
void invalidate_dcache_range(unsigned long start, unsigned long stop)
|
|
{
|
|
if (!check_cache_range(start, stop))
|
|
return;
|
|
|
|
while (start < stop) {
|
|
asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
|
|
start += CONFIG_SYS_CACHELINE_SIZE;
|
|
}
|
|
}
|
|
|
|
void flush_dcache_range(unsigned long start, unsigned long stop)
|
|
{
|
|
if (!check_cache_range(start, stop))
|
|
return;
|
|
|
|
while (start < stop) {
|
|
asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
|
|
start += CONFIG_SYS_CACHELINE_SIZE;
|
|
}
|
|
|
|
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
|
|
}
|
|
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
|
|
void invalidate_dcache_all(void)
|
|
{
|
|
}
|
|
|
|
void flush_dcache_all(void)
|
|
{
|
|
}
|
|
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
|
|
|
|
/*
|
|
* Stub implementations for l2 cache operations
|
|
*/
|
|
|
|
__weak void l2_cache_disable(void) {}
|
|
|
|
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
|
|
__weak void invalidate_l2_cache(void) {}
|
|
#endif
|
|
|
|
#ifndef CONFIG_SYS_ICACHE_OFF
|
|
/* Invalidate entire I-cache and branch predictor array */
|
|
void invalidate_icache_all(void)
|
|
{
|
|
unsigned long i = 0;
|
|
|
|
asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
|
|
}
|
|
#else
|
|
void invalidate_icache_all(void) {}
|
|
#endif
|
|
|
|
void enable_caches(void)
|
|
{
|
|
#ifndef CONFIG_SYS_ICACHE_OFF
|
|
icache_enable();
|
|
#endif
|
|
#ifndef CONFIG_SYS_DCACHE_OFF
|
|
dcache_enable();
|
|
#endif
|
|
}
|
|
|